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path: root/arch/x86/kernel/cpu/mce/amd.c
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2026-04-14Merge tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds1-67/+69
2026-04-14Merge tag 'x86-cleanups-2026-04-13' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-3/+3
2026-04-05x86/mce/amd: Filter bogus hardware errors on Zen3 clientsYazen Ghannam1-0/+8
2026-04-04x86/apic: Drop AMD Extended Interrupt LVT macrosNaveen N Rao (AMD)1-3/+3
2026-03-18x86/mce/amd: Check SMCA feature bit before accessing SMCA MSRsWilliam Roche1-6/+11
2026-03-11x86/mce, EDAC/mce_amd: Add new SMCA bank typesYazen Ghannam1-0/+21
2026-03-11x86/mce, EDAC/mce_amd: Update CS bank type namingYazen Ghannam1-1/+1
2026-03-11x86/mce, EDAC/mce_amd: Reorder SMCA bank type enumsYazen Ghannam1-67/+48
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds1-3/+3
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook1-3/+3
2025-11-21x86/mce: Handle AMD threshold interrupt stormsSmita Koralahalli1-0/+5
2025-11-21x86/mce: Add support for physical address valid bitAvadhut Naik1-3/+13
2025-11-21x86/mce: Save and use APEI corrected threshold limitYazen Ghannam1-2/+16
2025-11-05x86/mce/amd: Define threshold restart function for banksYazen Ghannam1-18/+19
2025-11-05x86/mce/amd: Remove redundant reset_block()Yazen Ghannam1-21/+7
2025-11-05x86/mce/amd: Support SMCA Corrected Error InterruptYazen Ghannam1-0/+17
2025-11-05x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systemsYazen Ghannam1-68/+53
2025-11-05x86/mce: Unify AMD DFR handler with MCA PollingYazen Ghannam1-98/+13
2025-11-05x86/mce: Unify AMD THR handler with MCA PollingYazen Ghannam1-28/+23
2025-09-11x86/mce: Add a clear_bank() helperYazen Ghannam1-0/+5
2025-09-11x86/mce: Separate global and per-CPU quirksYazen Ghannam1-0/+24
2025-09-11x86/mce: Define BSP-only SMCA initYazen Ghannam1-0/+6
2025-09-11x86/mce: Define BSP-only initYazen Ghannam1-3/+0
2025-09-05x86/mce: Remove __mcheck_cpu_init_early()Yazen Ghannam1-0/+4
2025-09-05x86/mce/amd: Put list_head in threshold_bankYazen Ghannam1-31/+12
2025-09-05x86/mce/amd: Remove smca_banks_mapYazen Ghannam1-41/+9
2025-09-05x86/mce/amd: Remove return value for mce_threshold_{create,remove}_device()Yazen Ghannam1-12/+10
2025-09-05x86/mce/amd: Rename threshold restart functionYazen Ghannam1-6/+6
2025-06-27x86/mce/amd: Fix threshold limit resetYazen Ghannam1-8/+7
2025-06-27x86/mce/amd: Add default names for MCA banks and blocksYazen Ghannam1-3/+10
2025-04-10x86/msr: Rename 'wrmsrl()' to 'wrmsrq()'Ingo Molnar1-4/+4
2025-04-10x86/msr: Rename 'rdmsrl()' to 'rdmsrq()'Ingo Molnar1-7/+7
2025-01-03x86/mce/amd: Remove shared threshold bank plumbingYazen Ghannam1-101/+26
2024-12-30x86/mce: Make several functions return boolQiuxu Zhuo1-5/+5
2024-10-31x86/MCE/AMD: Add support for new MCA_SYND{1,2} registersAvadhut Naik1-1/+4
2024-10-30x86/mce: Add wrapper for struct mce to export vendor specific infoAvadhut Naik1-13/+14
2024-08-01x86/mce: Rename mce_setup() to mce_prep_record()Yazen Ghannam1-1/+1
2024-02-15x86/cpu/amd: Provide a separate accessor for Node IDThomas Gleixner1-2/+2
2023-11-28x86/MCE/AMD: Add new MA_LLC, USR_DP, and USR_CP bank typesMuralidhara M K1-0/+6
2023-11-27x86/mce/amd, EDAC/mce_amd: Move long names to decoder moduleYazen Ghannam1-44/+30
2023-10-16x86/mce: Define amd_mce_usable_address()Yazen Ghannam1-0/+38
2023-10-16x86/MCE/AMD: Split amd_mce_is_memory_error()Yazen Ghannam1-6/+26
2023-08-09x86/apic: Nuke ack_APIC_irq()Dave Hansen1-1/+1
2023-07-22x86/MCE/AMD: Decrement threshold_bank refcount when removing threshold blocksYazen Ghannam1-2/+2
2023-06-05x86/MCE/AMD, EDAC/mce_amd: Decode UMC_V2 ECC errorsYazen Ghannam1-2/+4
2023-03-19x86/MCE/AMD: Use an u64 for bank_mapMuralidhara M K1-7/+7
2023-03-06x86/MCE/AMD: Make kobj_type structure constantThomas Weißschuh1-1/+1
2022-12-28x86/mce: Add support for Extended Physical Address MCA changesSmita Koralahalli1-0/+2
2022-12-28x86/mce: Define a function to extract ErrorAddr from MCA_ADDRSmita Koralahalli1-9/+1
2022-10-27x86/MCE/AMD: Clear DFR errors found in THR handlerYazen Ghannam1-13/+20
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