path: root/tools/perf/util/annotate-arch/annotate-powerpc.c

// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include "../annotate-data.h"
#include "../debug.h"
#include "../disasm.h"

#define PPC_OP(op)	(((op) >> 26) & 0x3F)
#define PPC_21_30(R)	(((R) >> 1) & 0x3ff)
#define PPC_22_30(R)	(((R) >> 1) & 0x1ff)

#define MINUS_EXT_XO_FORM	234
#define SUB_EXT_XO_FORM		232
#define	ADD_ZERO_EXT_XO_FORM	202
#define	SUB_ZERO_EXT_XO_FORM	200

static int arithmetic__scnprintf(const struct ins *ins, char *bf, size_t size,
		struct ins_operands *ops, int max_ins_name)
{
	return scnprintf(bf, size, "%-*s %s", max_ins_name, ins->name,
			ops->raw);
}

/*
 * Sets the fields: multi_regs and "mem_ref".
 * "mem_ref" is set for ops->source which is later used to
 * fill the objdump->memory_ref-char field. This ops is currently
 * used by powerpc and since binary instruction code is used to
 * extract opcode, regs and offset, no other parsing is needed here.
 *
 * Dont set multi regs for 4 cases since it has only one operand
 * for source:
 * - Add to Minus One Extended XO-form ( Ex: addme, addmeo )
 * - Subtract From Minus One Extended XO-form ( Ex: subfme )
 * - Add to Zero Extended XO-form ( Ex: addze, addzeo )
 * - Subtract From Zero Extended XO-form ( Ex: subfze )
 */
static int arithmetic__parse(const struct arch *arch __maybe_unused, struct ins_operands *ops,
		struct map_symbol *ms __maybe_unused, struct disasm_line *dl)
{
	int opcode = PPC_OP(dl->raw.raw_insn);

	ops->source.mem_ref = false;
	if (opcode == 31) {
		if ((opcode != MINUS_EXT_XO_FORM) && (opcode != SUB_EXT_XO_FORM) &&
		    (opcode != ADD_ZERO_EXT_XO_FORM) && (opcode != SUB_ZERO_EXT_XO_FORM))
			ops->source.multi_regs = true;
	}

	ops->target.mem_ref = false;
	ops->target.multi_regs = false;

	return 0;
}

static const struct ins_ops arithmetic_ops = {
	.parse     = arithmetic__parse,
	.scnprintf = arithmetic__scnprintf,
};

static int load_store__scnprintf(const struct ins *ins, char *bf, size_t size,
		struct ins_operands *ops, int max_ins_name)
{
	return scnprintf(bf, size, "%-*s %s", max_ins_name, ins->name,
			ops->raw);
}

/*
 * Sets the fields: multi_regs and "mem_ref".
 * "mem_ref" is set for ops->source which is later used to
 * fill the objdump->memory_ref-char field. This ops is currently
 * used by powerpc and since binary instruction code is used to
 * extract opcode, regs and offset, no other parsing is needed here
 */
static int load_store__parse(const struct arch *arch __maybe_unused, struct ins_operands *ops,
		struct map_symbol *ms __maybe_unused, struct disasm_line *dl __maybe_unused)
{
	ops->source.mem_ref = true;
	ops->source.multi_regs = false;
	/* opcode 31 is of X form */
	if (PPC_OP(dl->raw.raw_insn) == 31)
		ops->source.multi_regs = true;

	ops->target.mem_ref = false;
	ops->target.multi_regs = false;

	return 0;
}

static const struct ins_ops load_store_ops = {
	.parse     = load_store__parse,
	.scnprintf = load_store__scnprintf,
};

static const struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name)
{
	int i;
	const struct ins_ops *ops;

	/*
	 * - Interested only if instruction starts with 'b'.
	 * - Few start with 'b', but aren't branch instructions.
	 */
	if (name[0] != 'b'             ||
	    !strncmp(name, "bcd", 3)   ||
	    !strncmp(name, "brinc", 5) ||
	    !strncmp(name, "bper", 4))
		return NULL;

	ops = &jump_ops;

	i = strlen(name) - 1;
	if (i < 0)
		return NULL;

	/* ignore optional hints at the end of the instructions */
	if (name[i] == '+' || name[i] == '-')
		i--;

	if (name[i] == 'l' || (name[i] == 'a' && name[i-1] == 'l')) {
		/*
		 * if the instruction ends up with 'l' or 'la', then
		 * those are considered 'calls' since they update LR.
		 * ... except for 'bnl' which is branch if not less than
		 * and the absolute form of the same.
		 */
		if (strcmp(name, "bnl") && strcmp(name, "bnl+") &&
		    strcmp(name, "bnl-") && strcmp(name, "bnla") &&
		    strcmp(name, "bnla+") && strcmp(name, "bnla-"))
			ops = &call_ops;
	}
	if (name[i] == 'r' && name[i-1] == 'l')
		/*
		 * instructions ending with 'lr' are considered to be
		 * return instructions
		 */
		ops = &ret_ops;

	arch__associate_ins_ops(arch, name, ops);
	return ops;
}

struct insn_offset {
	const char	*name;
	int		value;
};

/*
 * There are memory instructions with opcode 31 which are
 * of X Form, Example:
 * ldx RT,RA,RB
 * ______________________________________
 * | 31 |  RT  |  RA |  RB |   21     |/|
 * --------------------------------------
 * 0    6     11    16    21         30 31
 *
 * But all instructions with opcode 31 are not memory.
 * Example: add RT,RA,RB
 *
 * Use bits 21 to 30 to check memory insns with 31 as opcode.
 * In ins_array below, for ldx instruction:
 * name => OP_31_XOP_LDX
 * value => 21
 */

static struct insn_offset ins_array[] = {
	{ .name = "OP_31_XOP_LXSIWZX",  .value = 12, },
	{ .name = "OP_31_XOP_LWARX",	.value = 20, },
	{ .name = "OP_31_XOP_LDX",	.value = 21, },
	{ .name = "OP_31_XOP_LWZX",	.value = 23, },
	{ .name = "OP_31_XOP_LDUX",	.value = 53, },
	{ .name = "OP_31_XOP_LWZUX",	.value = 55, },
	{ .name = "OP_31_XOP_LXSIWAX",  .value = 76, },
	{ .name = "OP_31_XOP_LDARX",    .value = 84, },
	{ .name = "OP_31_XOP_LBZX",	.value = 87, },
	{ .name = "OP_31_XOP_LVX",      .value = 103, },
	{ .name = "OP_31_XOP_LBZUX",    .value = 119, },
	{ .name = "OP_31_XOP_STXSIWX",  .value = 140, },
	{ .name = "OP_31_XOP_STDX",	.value = 149, },
	{ .name = "OP_31_XOP_STWX",	.value = 151, },
	{ .name = "OP_31_XOP_STDUX",	.value = 181, },
	{ .name = "OP_31_XOP_STWUX",	.value = 183, },
	{ .name = "OP_31_XOP_STBX",	.value = 215, },
	{ .name = "OP_31_XOP_STVX",     .value = 231, },
	{ .name = "OP_31_XOP_STBUX",	.value = 247, },
	{ .name = "OP_31_XOP_LHZX",	.value = 279, },
	{ .name = "OP_31_XOP_LHZUX",	.value = 311, },
	{ .name = "OP_31_XOP_LXVDSX",   .value = 332, },
	{ .name = "OP_31_XOP_LWAX",	.value = 341, },
	{ .name = "OP_31_XOP_LHAX",	.value = 343, },
	{ .name = "OP_31_XOP_LWAUX",	.value = 373, },
	{ .name = "OP_31_XOP_LHAUX",	.value = 375, },
	{ .name = "OP_31_XOP_STHX",	.value = 407, },
	{ .name = "OP_31_XOP_STHUX",	.value = 439, },
	{ .name = "OP_31_XOP_LXSSPX",   .value = 524, },
	{ .name = "OP_31_XOP_LDBRX",	.value = 532, },<