aboutsummaryrefslogtreecommitdiff
path: root/include/dt-bindings/gce/mt8195-gce.h
blob: dcfb302b8a5bc4baa239db2154c1f0a450d8e7f3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Jason-JH Lin <jason0jh.lin@mediatek.com>
 */

#ifndef _DT_BINDINGS_GCE_MT8195_H
#define _DT_BINDINGS_GCE_MT8195_H

/* assign timeout 0 also means default */
#define CMDQ_NO_TIMEOUT		0xffffffff
#define CMDQ_TIMEOUT_DEFAULT	1000

/* GCE thread priority */
#define CMDQ_THR_PRIO_LOWEST	0
#define CMDQ_THR_PRIO_1		1
#define CMDQ_THR_PRIO_2		2
#define CMDQ_THR_PRIO_3		3
#define CMDQ_THR_PRIO_4		4
#define CMDQ_THR_PRIO_5		5
#define CMDQ_THR_PRIO_6		6
#define CMDQ_THR_PRIO_HIGHEST	7

/* CPR count in 32bit register */
#define GCE_CPR_COUNT		1312

/* GCE subsys table */
#define SUBSYS_1400XXXX		0
#define SUBSYS_1401XXXX		1
#define SUBSYS_1402XXXX		2
#define SUBSYS_1c00XXXX		3
#define SUBSYS_1c01XXXX		4
#define SUBSYS_1c02XXXX		5
#define SUBSYS_1c10XXXX		6
#define SUBSYS_1c11XXXX		7
#define SUBSYS_1c12XXXX		8
#define SUBSYS_14f0XXXX		9
#define SUBSYS_14f1XXXX		10
#define SUBSYS_14f2XXXX		11
#define SUBSYS_1800XXXX		12
#define SUBSYS_1801XXXX		13
#define SUBSYS_1802XXXX		14
#define SUBSYS_1803XXXX		15
#define SUBSYS_1032XXXX		16
#define SUBSYS_1033XXXX		17
#define SUBSYS_1600XXXX		18
#define SUBSYS_1601XXXX		19
#define SUBSYS_14e0XXXX		20
#define SUBSYS_1c20XXXX		21
#define SUBSYS_1c30XXXX		22
#define SUBSYS_1c40XXXX		23
#define SUBSYS_1c50XXXX		24
#define SUBSYS_1c60XXXX		25

/* GCE General Purpose Register (GPR) support */
#define GCE_GPR_R00		0x0
#define GCE_GPR_R01		0x1
#define GCE_GPR_R02		0x2
#define GCE_GPR_R03		0x3
#define GCE_GPR_R04		0x4
#define GCE_GPR_R05		0x5
#define GCE_GPR_R06		0x6
#define GCE_GPR_R07		0x7
#define GCE_GPR_R08		0x8
#define GCE_GPR_R09		0x9
#define GCE_GPR_R10		0xa
#define GCE_GPR_R11		0xb
#define GCE_GPR_R12		0xc
#define GCE_GPR_R13		0xd
#define GCE_GPR_R14		0xe
#define GCE_GPR_R15		0xf

/* GCE hw event id */
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_0	1
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_1	2
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_2	3
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_3	4
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_4	5
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_5	6
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_6	7
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_7	8
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_8	9
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_9	10
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_10	11
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_11	12
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_12	13
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_13	14
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_14	15
#define CMDQ_EVENT_TRAW0_DMA_ERROR_INT	16
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_0	17
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_1	18
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_2	19
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_3	20
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_4	21
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_5	22
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_6	23
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_7	24
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_8	25
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_9	26
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_10	27
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_11	28
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_12	29
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_13	30
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_14	31
#define CMDQ_EVENT_TRAW1_DMA_ERROR_INT	32

#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_0	65
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_1	66
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_2	67
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_3	68
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_4	69
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_5	70
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_6	71
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_7	72
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_8	73
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_9	74
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_10	75
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_11	76
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_12	77
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_13	78
#define CMDQ_EVENT_DIP0_FRAME_DONE_P2_14	79
#define CMDQ_EVENT_DIP0_DMA_ERR	80
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_0	81
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_1	82
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_2	83
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_3	84
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_4	85
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_5	86
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_6	87
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_7	88
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_8	89
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_9	90
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_10	91
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_11	92
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_12	93
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_13	94
#define CMDQ_EVENT_PQA0_FRAME_DONE_P2_14	95
#define CMDQ_EVENT_PQA0_DMA_ERR	96
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_0	97
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_1	98
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_2	99
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_3	100
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_4	101
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_5	102
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_6	103
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_7	104
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_8	105
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_9	106
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_10	107
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_11	108
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_12	109
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_13	110
#define CMDQ_EVENT_PQB0_FRAME_DONE_P2_14	111
#define CMDQ_EVENT_PQB0_DMA_ERR	112
#define CMDQ_EVENT_DIP0_DUMMY_0	113
#define CMDQ_EVENT_DIP0_DUMMY_1	114
#define CMDQ_EVENT_DIP0_DUMMY_2	115
#define CMDQ_EVENT_DIP0_DUMMY_3	116
#define CMDQ_EVENT_WPE0_EIS_GCE_FRAME_DONE	117
#define CMDQ_EVENT_WPE0_EIS_DONE_SYNC_OUT	118
#define CMDQ_EVENT_WPE0_TNR_GCE_FRAME_DONE	119
#define CMDQ_EVENT_WPE0_TNR_DONE_SYNC_OUT	120
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_0	121
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_1	122
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_2	123
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_3	124
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_4	125
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_5	126
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_6	127
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_7	128
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_8	129
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_9	130
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_10	131
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_11	132
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_12	133
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_13	134
#define CMDQ_EVENT_WPE0_EIS_FRAME_DONE_P2_14	135
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_0	136
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_1	137
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_2	138
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_3	139
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_4	140
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_5	141
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_6	142
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_7	143
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_8	144
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_9	145
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_10	146
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_11	147
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_12	148
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_13	149
#define CMDQ_EVENT_WPE0_TNR_FRAME_DONE_P2_14	150
#define CMDQ_EVENT_WPE0_DUMMY_0	151
#define CMDQ_EVENT_IMGSYS_IPE_DUMMY	152
#define CMDQ_EVENT_IMGSYS_IPE_FDVT_DONE	153
#define CMDQ_EVENT_IMGSYS_IPE_ME_DONE	154
#define CMDQ_EVENT_IMGSYS_IPE_DVS_DONE	155
#define CMDQ_EVENT_IMGSYS_IPE_DVP_DONE	156

#define CMDQ_EVENT_TPR_0	194
#define CMDQ_EVENT_TPR_1	195
#define CMDQ_EVENT_TPR_2	196
#define CMDQ_EVENT_TPR_3	197
#define CMDQ_EVENT_TPR_4	198
#define CMDQ_EVENT_TPR_5	199
#define CMDQ_EVENT_TPR_6	200
#define CMDQ_EVENT_TPR_7	201
#define CMDQ_EVENT_TPR_8	202
#define CMDQ_EVENT_TPR_9	203
#define CMDQ_EVENT_TPR_10	204
#define CMDQ_EVENT_TPR_11	205
#define CMDQ_EVENT_TPR_12	206
#define CMDQ_EVENT_TPR_13	207
#define CMDQ_EVENT_TPR_14	208
#define CMDQ_EVENT_TPR_15	209
#define CMDQ_EVENT_TPR_16	210
#define CMDQ_EVENT_TPR_17	211
#define CMDQ_EVENT_TPR_18	212
#define CMDQ_EVENT_TPR_19	213
#define CMDQ_EVENT_TPR_20	214
#define CMDQ_EVENT_TPR_21	215
#define CMDQ_EVENT_TPR_22	216
#define CMDQ_EVENT_TPR_23	217
#define CMDQ_EVENT_TPR_24	218
#define CMDQ_EVENT_TPR_25	219
#define CMDQ_EVENT_TPR_26	220
#define CMDQ_EVENT_TPR_27	221
#define CMDQ_EVENT_TPR_28	222
#define CMDQ_EVENT_TPR_29	223
#define CMDQ_EVENT_TPR_30	224
#define CMDQ_EVENT_TPR_31	225
#define CMDQ_EVENT_TPR_TIMEOUT_0	226
#define CMDQ_EVENT_TPR_TIMEOUT_1	227
#define CMDQ_EVENT_TPR_TIMEOUT_2	228
#define CMDQ_EVENT_TPR_TIMEOUT_3	229
#define CMDQ_EVENT_TPR_TIMEOUT_4	230
#define CMDQ_EVENT_TPR_TIMEOUT_5	231
#define CMDQ_EVENT_TPR_TIMEOUT_6	232
#define CMDQ_EVENT_TPR_TIMEOUT_7	233
#define CMDQ_EVENT_TPR_TIMEOUT_8	234
#define CMDQ_EVENT_TPR_TIMEOUT_9	235
#define CMDQ_EVENT_TPR_TIMEOUT_10	236
#define CMDQ_EVENT_TPR_TIMEOUT_11	237
#define CMDQ_EVENT_TPR_TIMEOUT_12	238
#define CMDQ_EVENT_TPR_TIMEOUT_13	239
#define CMDQ_EVENT_TPR_TIMEOUT_14	240
#define CMDQ_EVENT_TPR_TIMEOUT_15	241

#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF	256
#define CMDQ_EVENT_VPP0_MDP_FG_SOF	257
#define CMDQ_EVENT_VPP0_STITCH_SOF	258
#define CMDQ_EVENT_VPP0_MDP_HDR_SOF	259
#define CMDQ_EVENT_VPP0_MDP_AAL_SOF	260
#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF	261
#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF	262
#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF	263
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF	264
#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF	265
#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF	266
#define CMDQ_EVENT_VPP0_MDP_WROT_SOF	267

#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE	269
#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE	270
#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF	271
#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE	272

#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE	288
#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE	289
#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE	290
#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE	291
#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE	292
#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE	293
#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE	294
#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE	295
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE	296
#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE	297
#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE	298
#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE	299

#define CMDQ_EVENT_VPP0_STREAM_DONE_0	320
#define CMDQ_EVENT_VPP0_STREAM_DONE_1	321
#define CMDQ_EVENT_VPP0_STREAM_DONE_2	322
#define CMDQ_EVENT_VPP0_STREAM_DONE_3	323
#define CMDQ_EVENT_VPP0_STREAM_DONE_4	324
#define CMDQ_EVENT_VPP0_STREAM_DONE_5	325
#define CMDQ_EVENT_VPP0_STREAM_DONE_6	326
#define CMDQ_EVENT_VPP0_STREAM_DONE_7	327
#define CMDQ_EVENT_VPP0_STREAM_DONE_8	328
#define CMDQ_EVENT_VPP0_STREAM_DONE_9	329
#define CMDQ_EVENT_VPP0_STREAM_DONE_10	330
#define CMDQ_EVENT_VPP0_STREAM_DONE_11	331
#define CMDQ_EVENT_VPP0_STREAM_DONE_12	332
#define CMDQ_EVENT_VPP0_STREAM_DONE_13	333
#define CMDQ_EVENT_VPP0_STREAM_DONE_14	334
#define CMDQ_EVENT_VPP0_STREAM_DONE_15	335
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_0	336
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_1	337
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_2	338
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_3	339
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_4	340
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_5	341
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_6	342
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_7	343
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_8	344
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_9	345
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_10	346
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_11	347
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_12	348
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_13	349
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_14	350
#define CMDQ_EVENT_VPP0_BUF_UNDERRUN_15	351
#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE	352
#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID	353
#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE	354
#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE	355

#define CMDQ_EVENT_VPP1_HDMI_META_SOF		384
#define CMDQ_EVENT_VPP1_DGI_SOF			385
#define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF		386
#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF	387
#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF	388
#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF	389
#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF	390
#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF	391
#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF	392
#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF	393
#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF	394
#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF	395
#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF	396
#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF	397
#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF	398
#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF	399
#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF	400
#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF	401
#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF	402
#define CMDQ_EVENT_VPP1_SVPP1_TDSHP_SOF		403
#define CMDQ_EVENT_VPP1_SVPP2_TDSHP_SOF		404
#define CMDQ_EVENT_VPP1_SVPP3_TDSHP_SOF		405
#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF	406
#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF	407
#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF	408
#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF	409
#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF	410
#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF	411
#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF	412
#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF	413
#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF	414
#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF	415
#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF	416
#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF	417
#define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF	418
#define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF	419
#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF	420
#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF	421
#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF	422
#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF	423
#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE	424
#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE	425
#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE	426
#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE	427
#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE	428
#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE	429
#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE	430
#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE	431
#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE	432
#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE	433
#define CMDQ_EVENT_VPP1_FRAME_DONE_10	434
#define CMDQ_EVENT_VPP1_FRAME_DONE_11	435
#define CMDQ_EVENT_VPP1_FRAME_DONE_12	436
#define CMDQ_EVENT_VPP1_FRAME_DONE_13	437
#define CMDQ_EVENT_VPP1_FRAME_DONE_14	438
#define CMDQ_EVENT_VPP1_STREAM_DONE_0	439
#define CMDQ_EVENT_VPP1_STREAM_DONE_1	440
#define CMDQ_EVENT_VPP1_STREAM_DONE_2	441
#define CMDQ_EVENT_VPP1_STREAM_DONE_3	442
#define CMDQ_EVENT_VPP1_STREAM_DONE_4	443
#define CMDQ_EVENT_VPP1_STREAM_DONE_5	444
#define CMDQ_EVENT_VPP1_STREAM_DONE_6	445
#define CMDQ_EVENT_VPP1_STREAM_DONE_7	446
#define CMDQ_EVENT_VPP1_STREAM_DONE_8	447
#define CMDQ_EVENT_VPP1_STREAM_DONE_9	448
#define CMDQ_EVENT_VPP1_STREAM_DONE_10	449
#define CMDQ_EVENT_VPP1_STREAM_DONE_11	450
#define CMDQ_EVENT_VPP1_STREAM_DONE_12	451
#define CMDQ_EVENT_VPP1_STREAM_DONE_13	452
#define CMDQ_EVENT_VPP1_STREAM_DONE_14	453
#define CMDQ_EVENT_VPP1_STREAM_DONE_15	454
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_0	455
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_1	456
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_2	457
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_3	458
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_4	459
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_5	460
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_6	461
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_7	462
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_8	463
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_9	464
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_10	465
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_11	466
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_12	467
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_13	468
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_14	469
#define CMDQ_EVENT_VPP1_MDP_BUF_UNDERRUN_15	470
#define CMDQ_EVENT_VPP1_DGI_0	471
#define CMDQ_EVENT_VPP1_DGI_1	472
#define CMDQ_EVENT_VPP1_DGI_2	473
#define CMDQ_EVENT_VPP1_DGI_3	474
#define CMDQ_EVENT_VPP1_DGI_4	475
#define CMDQ_EVENT_VPP1_DGI_5	476
#define CMDQ_EVENT_VPP1_DGI_6	477
#define CMDQ_EVENT_VPP1_DGI_7	478
#define CMDQ_EVENT_VPP1_DGI_8	479
#define CMDQ_EVENT_VPP1_DGI_9	480
#define CMDQ_EVENT_VPP1_DGI_10	481
#define CMDQ_EVENT_VPP1_DGI_11	482
#define CMDQ_EVENT_VPP1_DGI_12	483
#define CMDQ_EVENT_VPP1_DGI_13	484
#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE	485
#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE	486
#define CMDQ_EVENT_VPP1_MDP_OVL_FRAME_RESET_DONE_PULSE	487
#define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI	488
#define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI	489
#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE	490
#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE	491
#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE	492
#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE	493
#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE	494
#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE	495

#define CMDQ_EVENT_VDO0_DISP_OVL0_SOF	512
#define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF	513
#define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF	514
#define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF	515
#define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF	516
#define CMDQ_EVENT_VDO0_DISP_AAL0_SOF	517
#define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF	518
#define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF	519
#define CMDQ_EVENT_VDO0_DSI0_SOF	520
#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF	521
#define CMDQ_EVENT_VDO0_DISP_OVL1_SOF	522
#define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF	523
#define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF	524
#define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF	525
#define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF	526
#define CMDQ_EVENT_VDO0_DISP_AAL1_SOF	527
#define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF	528
#define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF	529
#define CMDQ_EVENT_VDO0_DSI1_SOF	530
#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF	531
#define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF	532
#define CMDQ_EVENT_VDO0_DP_INTF0_SOF	533
#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF	534
#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF	535
#define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF	536
#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF	537
#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF	538