path: root/drivers/spi/spi-atcspi200.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Andes ATCSPI200 SPI Controller
 *
 * Copyright (C) 2025 Andes Technology Corporation.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/dev_printk.h>
#include <linux/dmaengine.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/jiffies.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>

/* Register definitions  */
#define ATCSPI_TRANS_FMT	0x10	/* SPI transfer format register */
#define ATCSPI_TRANS_CTRL	0x20	/* SPI transfer control register */
#define ATCSPI_CMD		0x24	/* SPI command register */
#define ATCSPI_ADDR		0x28	/* SPI address register */
#define ATCSPI_DATA		0x2C	/* SPI data register */
#define ATCSPI_CTRL		0x30	/* SPI control register */
#define ATCSPI_STATUS		0x34	/* SPI status register */
#define ATCSPI_TIMING		0x40	/* SPI interface timing register */
#define ATCSPI_CONFIG		0x7C	/* SPI configuration register */

/* Transfer format register */
#define TRANS_FMT_CPHA		BIT(0)
#define TRANS_FMT_CPOL		BIT(1)
#define TRANS_FMT_DATA_MERGE_EN	BIT(7)
#define TRANS_FMT_DATA_LEN_MASK	GENMASK(12, 8)
#define TRANS_FMT_ADDR_LEN_MASK	GENMASK(17, 16)
#define TRANS_FMT_DATA_LEN(x)	FIELD_PREP(TRANS_FMT_DATA_LEN_MASK, (x) - 1)
#define TRANS_FMT_ADDR_LEN(x)	FIELD_PREP(TRANS_FMT_ADDR_LEN_MASK, (x) - 1)

/* Transfer control register */
#define TRANS_MODE_MASK		GENMASK(27, 24)
#define TRANS_MODE_W_ONLY	FIELD_PREP(TRANS_MODE_MASK, 1)
#define TRANS_MODE_R_ONLY	FIELD_PREP(TRANS_MODE_MASK, 2)
#define TRANS_MODE_NONE_DATA	FIELD_PREP(TRANS_MODE_MASK, 7)
#define TRANS_MODE_DMY_READ	FIELD_PREP(TRANS_MODE_MASK, 9)
#define TRANS_FIELD_DECNZ(m, x)	((x) ? FIELD_PREP(m, (x) - 1) : 0)
#define TRANS_RD_TRANS_CNT(x)	TRANS_FIELD_DECNZ(GENMASK(8, 0), x)
#define TRANS_DUMMY_CNT(x)	TRANS_FIELD_DECNZ(GENMASK(10, 9), x)
#define TRANS_WR_TRANS_CNT(x)	TRANS_FIELD_DECNZ(GENMASK(20, 12), x)
#define TRANS_DUAL_QUAD(x)	FIELD_PREP(GENMASK(23, 22), (x))
#define TRANS_ADDR_FMT		BIT(28)
#define TRANS_ADDR_EN		BIT(29)
#define TRANS_CMD_EN		BIT(30)

/* Control register */
#define CTRL_SPI_RST		BIT(0)
#define CTRL_RX_FIFO_RST	BIT(1)
#define CTRL_TX_FIFO_RST	BIT(2)
#define CTRL_RX_DMA_EN		BIT(3)
#define CTRL_TX_DMA_EN		BIT(4)

/* Status register */
#define ATCSPI_ACTIVE		BIT(0)
#define ATCSPI_RX_EMPTY		BIT(14)
#define ATCSPI_TX_FULL		BIT(23)

/* Interface timing setting */
#define TIMING_SCLK_DIV_MASK	GENMASK(7, 0)
#define TIMING_SCLK_DIV_MAX	0xFE

/* Configuration register */
#define RXFIFO_SIZE(x)		FIELD_GET(GENMASK(3, 0), (x))
#define TXFIFO_SIZE(x)		FIELD_GET(GENMASK(7, 4), (x))

/* driver configurations */
#define ATCSPI_MAX_TRANS_LEN	512
#define ATCSPI_MAX_SPEED_HZ	50000000
#define ATCSPI_RDY_TIMEOUT_US	1000000
#define ATCSPI_XFER_TIMEOUT(n)	((n) * 10)
#define ATCSPI_MAX_CS_NUM	1
#define ATCSPI_DMA_THRESHOLD	256
#define ATCSPI_BITS_PER_UINT	8
#define ATCSPI_DATA_MERGE_EN	1
#define ATCSPI_DMA_SUPPORT	1

/**
 * struct atcspi_dev - Andes ATCSPI200 SPI controller private data
 * @host:           Pointer to the SPI controller structure.
 * @mutex_lock:     A mutex to protect concurrent access to the controller.
 * @dma_completion: A completion to signal the end of a DMA transfer.
 * @dev:            Pointer to the device structure.
 * @regmap:         Register map for accessing controller registers.
 * @clk:            Pointer to the controller's functional clock.
 * @dma_addr:       The physical address of the SPI data register for DMA.
 * @clk_rate:       The cached frequency of the functional clock.
 * @sclk_rate:      The target frequency for the SPI clock (SCLK).
 * @txfifo_size:    The size of the transmit FIFO in bytes.
 * @rxfifo_size:    The size of the receive FIFO in bytes.
 * @data_merge:     A flag indicating if the data merge mode is enabled for
 *                  the current transfer.
 * @use_dma:        Enable DMA mode if ATCSPI_DMA_SUPPORT is set and DMA is
 *                  successfully configured.
 */
struct atcspi_dev {
	struct spi_controller	*host;
	struct mutex		mutex_lock;
	struct completion	dma_completion;
	struct device		*dev;
	struct regmap		*regmap;
	struct clk		*clk;
	dma_addr_t		dma_addr;
	unsigned int		clk_rate;
	unsigned int		sclk_rate;
	unsigned int		txfifo_size;
	unsigned int		rxfifo_size;
	bool			data_merge;
	bool			use_dma;
};

static int atcspi_wait_fifo_ready(struct atcspi_dev *spi,
				  enum spi_mem_data_dir dir)
{
	unsigned int val;
	unsigned int mask;
	int ret;

	mask = (dir == SPI_MEM_DATA_OUT) ? ATCSPI_TX_FULL : ATCSPI_RX_EMPTY;
	ret = regmap_read_poll_timeout(spi->regmap,
				       ATCSPI_STATUS,
				       val,
				       !(val & mask),
				       0,
				       ATCSPI_RDY_TIMEOUT_US);
	if (ret)
		dev_info(spi->dev, "Timed out waiting for FIFO ready\n");

	return ret;
}

static int atcspi_xfer_data_poll(struct atcspi_dev *spi,
				 const struct spi_mem_op *op)
{
	void *rx_buf = op->data.buf.in;
	const void *tx_buf = op->data.buf.out;
	unsigned int val;
	int trans_bytes = op->data.nbytes;
	int num_byte;
	int ret = 0;

	num_byte = spi->data_merge ? 4 : 1;
	while (trans_bytes) {
		if (op->data.dir == SPI_MEM_DATA_OUT) {
			ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_OUT);
			if (ret)
				return ret;

			if (spi->data_merge)
				val = *(unsigned int *)tx_buf;
			else
				val = *(unsigned char *)tx_buf;
			regmap_write(spi->regmap, ATCSPI_DATA, val);
			tx_buf = (unsigned char *)tx_buf + num_byte;
		} else {
			ret = atcspi_wait_fifo_ready(spi, SPI_MEM_DATA_IN);
			if (ret)
				return ret;

			regmap_read(spi->regmap, ATCSPI_DATA, &val);
			if (spi->data_merge)
				*(unsigned int *)rx_buf = val;
			else
				*(unsigned char *)rx_buf = (unsigned char)val;
			rx_buf = (unsigned char *)rx_buf + num_byte;
		}
		trans_bytes -= num_byte;
	}

	return ret;
}

static void atcspi_set_trans_ctl(struct atcspi_dev *spi,
				 const struct spi_mem_op *op)
{
	unsigned int tc = 0;

	if (op->cmd.nbytes)
		tc |= TRANS_CMD_EN;
	if (op->addr.nbytes)
		tc |= TRANS_ADDR_EN;
	if (op->addr.buswidth > 1)
		tc |= TRANS_ADDR_FMT;
	if (op->data.nbytes) {
		unsigned int width_code;

		width_code = ffs(op->data.buswidth) - 1;
		if (unlikely(width_code > 3)) {
			WARN_ON_ONCE(1);
			width_code = 0;
		}
		tc |= TRANS_DUAL_QUAD(width_code);

		if (op->data.dir == SPI_MEM_DATA_IN) {
			if (op->dummy.nbytes)
				tc |= TRANS_MODE_DMY_READ |
				      TRANS_DUMMY_CNT(op->dummy.nbytes);
			else
				tc |= TRANS_MODE_R_ONLY;
			tc |= TRANS_RD_TRANS_CNT(op->data.nbytes);
		} else {
			tc |= TRANS_MODE_W_ONLY |
			      TRANS_WR_TRANS_CNT(op->data.nbytes);
		}
	} else {
		tc |= TRANS_MODE_NONE_DATA;
	}
	regmap_write(spi->regmap, ATCSPI_TRANS_CTRL, tc);
}

static void atcspi_set_trans_fmt(struct atcspi_dev *spi,
				 const struct spi_mem_op *op)
{
	unsigned int val;

	regmap_read(spi->regmap, ATCSPI_TRANS_FMT, &val);
	if (op->data.nbytes) {
		if (ATCSPI_DATA_MERGE_EN && ATCSPI_BITS_PER_UINT == 8 &&
		    !(op->data.nbytes % 4)) {
			val |= TRANS_FMT_DATA_MERGE_EN;
			spi->data_merge = true;
		} else {
			val &= ~TRANS_FMT_DATA_MERGE_EN;
			spi->data_merge = false;
		}
	}

	val = (val & ~TRANS_FMT_ADDR_LEN_MASK) |
	      TRANS_FMT_ADDR_LEN(op->addr.nbytes);
	regmap_write(spi->regmap, ATCSPI_TRANS_FMT, val