path: root/drivers/phy/starfive/phy-jh7110-dphy-tx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * DPHY TX driver for the StarFive JH7110 SoC
 *
 * Copyright (C) 2023 StarFive Technology Co., Ltd.
 * Author: Keith Zhao <keith.zhao@starfivetech.com>
 * Author: Shengyang Chen <shengyang.chen@starfivetech.com>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>

#define STF_DPHY_APBIFSAIF_SYSCFG(x)			(x)

#define STF_DPHY_AON_POWER_READY_N_ACTIVE		0
#define STF_DPHY_AON_POWER_READY_N			BIT(0)
#define STF_DPHY_CFG_L0_SWAP_SEL			GENMASK(14, 12)
#define STF_DPHY_CFG_L1_SWAP_SEL			GENMASK(17, 15)
#define STF_DPHY_CFG_L2_SWAP_SEL			GENMASK(20, 18)
#define STF_DPHY_CFG_L3_SWAP_SEL			GENMASK(23, 21)
#define STF_DPHY_CFG_L4_SWAP_SEL			GENMASK(26, 24)
#define STF_DPHY_RGS_CDTX_PLL_UNLOCK			BIT(18)
#define STF_DPHY_RG_CDTX_L0N_HSTX_RES			GENMASK(23, 19)
#define STF_DPHY_RG_CDTX_L0P_HSTX_RES			GENMASK(28, 24)

#define STF_DPHY_RG_CDTX_L1P_HSTX_RES			GENMASK(9, 5)
#define STF_DPHY_RG_CDTX_L2N_HSTX_RES			GENMASK(14, 10)
#define STF_DPHY_RG_CDTX_L2P_HSTX_RES			GENMASK(19, 15)
#define STF_DPHY_RG_CDTX_L3N_HSTX_RES			GENMASK(24, 20)
#define STF_DPHY_RG_CDTX_L3P_HSTX_RES			GENMASK(29, 25)

#define STF_DPHY_RG_CDTX_L4N_HSTX_RES			GENMASK(4, 0)
#define STF_DPHY_RG_CDTX_L4P_HSTX_RES			GENMASK(9, 5)
#define STF_DPHY_RG_CDTX_PLL_FBK_FRA			GENMASK(23, 0)

#define STF_DPHY_RG_CDTX_PLL_FBK_INT			GENMASK(8, 0)
#define STF_DPHY_RG_CDTX_PLL_FM_EN			BIT(9)
#define STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN		BIT(10)
#define STF_DPHY_RG_CDTX_PLL_PRE_DIV			GENMASK(12, 11)

#define STF_DPHY_RG_CDTX_PLL_SSC_EN			BIT(18)

#define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME		GENMASK(7, 0)
#define STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME		GENMASK(15, 8)
#define STF_DPHY_RG_CLANE_HS_PRE_TIME			GENMASK(23, 16)
#define STF_DPHY_RG_CLANE_HS_TRAIL_TIME			GENMASK(31, 24)

#define STF_DPHY_RG_CLANE_HS_ZERO_TIME			GENMASK(7, 0)
#define STF_DPHY_RG_DLANE_HS_PRE_TIME			GENMASK(15, 8)
#define STF_DPHY_RG_DLANE_HS_TRAIL_TIME			GENMASK(23, 16)
#define STF_DPHY_RG_DLANE_HS_ZERO_TIME			GENMASK(31, 24)

#define STF_DPHY_RG_EXTD_CYCLE_SEL			GENMASK(2, 0)
#define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME		GENMASK(31, 0)

#define STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL		GENMASK(2, 1)
#define STF_DPHY_SCFG_PPI_C_READY_SEL			GENMASK(4, 3)

#define STF_DPHY_REFCLK_IN_SEL				GENMASK(28, 26)
#define STF_DPHY_RESETB					BIT(29)

#define STF_DPHY_REFCLK_12M				1
#define STF_DPHY_BITRATE_ALIGN				10000000

#define STF_MAP_LANES_NUM				5

#define STF_DPHY_LSHIFT_16(x)				(FIELD_PREP(GENMASK(23, 16), (x)))
#define STF_DPHY_LSHIFT_8(x)				(FIELD_PREP(GENMASK(15, 8), (x)))

#define STF_DPHY_HW_DELAY_US				200
#define STF_DPHY_HW_TIMEOUT_US				5000

struct stf_dphy_config {
	unsigned long bitrate;
	u32 pll_fbk_int;
	u32 pll_fbk_fra_val;
	u32 extd_cycle_sel;
	u32 dlane_hs_pre_time;
	u32 dlane_hs_zero_time;
	u32 dlane_hs_trail_time;
	u32 clane_hs_pre_time;
	u32 clane_hs_zero_time;
	u32 clane_hs_trail_time;
	u32 clane_hs_clk_pre_time;
	u32 clane_hs_clk_post_time;
};

static const struct stf_dphy_config reg_configs[] = {
	{160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
	{170000000, 0x71, 0x55, 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d},
	{180000000, 0x78, 0x0, 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e},
	{190000000, 0x7e, 0xaa, 0x3, 0xc, 0x1a, 0x12, 0x6, 0x33, 0xe, 0x7, 0x3e},
	{200000000, 0x85, 0x55, 0x3, 0xc, 0x1b, 0x13, 0x7, 0x35, 0xf, 0x7, 0x3f},
	{320000000, 0x6a, 0xaa, 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23},
	{330000000, 0x6e, 0x0, 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23},
	{340000000, 0x71, 0x55, 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23},
	{350000000, 0x74, 0xaa, 0x2, 0x9, 0x15, 0x10, 0x6, 0x2f, 0xe, 0x3, 0x24},
	{360000000, 0x78, 0x0, 0x2, 0x9, 0x16, 0x10, 0x6, 0x30, 0xe, 0x3, 0x24},
	{370000000, 0x7b, 0x55, 0x2, 0x9, 0x17, 0x10, 0x6, 0x32, 0xe, 0x3, 0x24},
	{380000000, 0x7e, 0xaa, 0x2, 0xa, 0x17, 0x10, 0x6, 0x33, 0xe, 0x3, 0x24},
	{390000000, 0x82, 0x0, 0x2, 0xa, 0x17, 0x11, 0x6, 0x35, 0xf, 0x3, 0x25},
	{400000000, 0x85, 0x55, 0x2, 0xa, 0x18, 0x11, 0x7, 0x35, 0xf, 0x3, 0x25},
	{410000000, 0x88, 0xaa, 0x2, 0xa, 0x19, 0x11, 0x7, 0x37, 0xf, 0x3, 0x25},
	{420000000, 0x8c, 0x0, 0x2, 0xa, 0x19, 0x12, 0x7, 0x38, 0x10, 0x3, 0x26},
	{430000000, 0x8f, 0x55, 0x2, 0xb, 0x19, 0x12, 0x7, 0x39, 0x10, 0x3, 0x26},
	{440000000, 0x92, 0xaa, 0x2, 0xb, 0x1a, 0x12, 0x7, 0x3b, 0x10, 0x3, 0x26},
	{450000000, 0x96, 0x0, 0x2, 0xb, 0x1b, 0x12, 0x8, 0x3c, 0x10, 0x3, 0x26},
	{460000000, 0x99, 0x55, 0x2, 0xb, 0x1b, 0x13, 0x8, 0x3d, 0x11, 0x3, 0x27},
	{470000000, 0x9c, 0xaa, 0x2, 0xc, 0x1b, 0x13, 0x8, 0x3e, 0x11, 0x3, 0x27},
	{480000000, 0xa0, 0x27, 0x2, 0xc, 0x1c, 0x13, 0x8, 0x40, 0x11, 0x3, 0x27},
	{490000000, 0xa3, 0x55, 0x2, 0xc, 0x1d, 0x14, 0x8, 0x42, 0x12, 0x3, 0x28},
	{500000000, 0xa6, 0xaa, 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28},
	{510000000, 0xaa, 0x0, 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28},
	{520000000, 0xad, 0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29},
	{530000000, 0xb0, 0xaa, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29},
	{540000000, 0xb4, 0x0, 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29},
	{550000000, 0xb7, 0x55, 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a},
	{560000000, 0xba, 0xaa, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4a, 0x14, 0x3, 0x2a},
	{570000000, 0xbe, 0x0, 0x2, 0xe, 0x20, 0x16, 0xa, 0x4c, 0x14, 0x3, 0x2a},
	{580000000, 0xc1, 0x55, 0x2, 0xe, 0x21, 0x16, 0xa, 0x4d, 0x14, 0x3, 0x2a},
	{590000000, 0xc4, 0xaa, 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b},
	{600000000, 0xc8, 0x0, 0x2, 0xe, 0x23, 0x17, 0xa, 0x50, 0x15, 0x3, 0x2b},
	{610000000, 0xcb, 0x55, 0x2, 0xf, 0x22, 0x17, 0xb, 0x50, 0x15, 0x3, 0x2b},
	{620000000, 0xce