path: root/drivers/phy/spacemit/phy-k1-pcie.c

// SPDX-License-Identifier: GPL-2.0
/*
 * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver
 *
 * Copyright (C) 2025 by RISCstar Solutions Corporation.  All rights reserved.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include <dt-bindings/phy/phy.h>

/*
 * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver
 * supports their PHYs.
 *
 * The PHY for PCIe port A is different from the PHYs for ports B and C:
 * - It has one lane, while ports B and C have two
 * - It is a combo PHY can be used for PCIe or USB 3
 * - It can automatically calibrate PCIe TX and RX termination settings
 *
 * The PHY functionality for PCIe ports B and C is identical:
 * - They have two PCIe lanes (but can be restricted to 1 via device tree)
 * - They are used for PCIe only
 * - They are configured using TX and RX values computed for port A
 *
 * A given board is designed to use the combo PHY for either PCIe or USB 3.
 * Whether the combo PHY is configured for PCIe or USB 3 is specified in
 * device tree using a phandle plus an argument.  The argument indicates
 * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3).
 *
 * Each PHY has a reset that it gets and deasserts during initialization.
 * Each depends also on other clocks and resets provided by the controller
 * hardware (PCIe or USB) it is associated with.  The controller drivers
 * are required to enable any clocks and de-assert any resets that affect
 * PHY operation.  In addition each PHY implements an internal PLL, driven
 * by an external (24 MHz) oscillator.
 *
 * PCIe PHYs must be programmed with RX and TX calibration values.  The
 * combo PHY is the only one that can determine these values.  They are
 * determined by temporarily enabling the combo PHY in PCIe mode at probe
 * time (if necessary).  This calibration only needs to be done once, and
 * when it has completed the TX and RX values are saved.
 *
 * To allow the combo PHY to be enabled for calibration, the resets and
 * clocks it uses in PCIe mode must be supplied.
 */

struct k1_pcie_phy {
	struct device *dev;		/* PHY provider device */
	struct phy *phy;
	void __iomem *regs;
	u32 pcie_lanes;			/* Max (1 or 2) unless limited by DT */
	struct clk *pll;
	struct clk_hw pll_hw;		/* Private PLL clock */

	/* The remaining fields are only used for the combo PHY */
	u32 type;			/* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
	struct regmap *pmu;		/* MMIO regmap (no errors) */
};

#define CALIBRATION_TIMEOUT		500000	/* For combo PHY (usec) */
#define PLL_TIMEOUT			500000	/* For PHY PLL lock (usec) */
#define POLL_DELAY			500	/* Time between polls (usec) */

/* Selecting the combo PHY operating mode requires APMU regmap access */
#define SYSCON_APMU			"spacemit,apmu"

/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */

#define PMUA_USB_PHY_CTRL0			0x0110
#define COMBO_PHY_SEL			BIT(3)	/* 0: PCIe; 1: USB 3 */

#define PCIE_CLK_RES_CTRL			0x03cc
#define PCIE_APP_HOLD_PHY_RST		BIT(30)

/* PHY register space */

/* Offset between lane 0 and lane 1 registers when there are two */
#define PHY_LANE_OFFSET				0x0400

/* PHY PLL configuration */
#define PCIE_PU_ADDR_CLK_CFG			0x0008
#define PLL_READY			BIT(0)		/* read-only */
#define CFG_INTERNAL_TIMER_ADJ		GENMASK(10, 7)
#define TIMER_ADJ_USB		0x2
#define TIMER_ADJ_PCIE		0x6
#define CFG_SW_PHY_INIT_DONE		BIT(11)	/* We set after PLL config */

#define PCIE_RC_DONE_STATUS			0x0018
#define CFG_FORCE_RCV_RETRY		BIT(10)		/* Used for PCIe */

/* PCIe PHY lane calibration; assumes 24MHz input clock */
#define PCIE_RC_CAL_REG2			0x0020
#define RC_CAL_TOGGLE			BIT(22)
#define CLKSEL				GENMASK(31, 29)
#define CLKSEL_24M		0x3

/* Additional PHY PLL configuration (USB 3 and PCIe) */
#define PCIE_PU_PLL_1				0x0048
#define REF_100_WSSC			BIT(12)	/* 1: input is 100MHz, SSC */
#define FREF_SEL			GENMASK(15, 13)
#define FREF_24M		0x1
#define SSC_DEP_SEL			GENMASK(19, 16)
#define SSC_DEP_NONE		0x0
#define SSC_DEP_5000PPM		0xa

/* PCIe PHY configuration */
#define PCIE_PU_PLL_2				0x004c
#define GEN_REF100			BIT(4)	/* 1: generate 100MHz clk */

#define PCIE_RX_REG1				0x0050
#define EN_RTERM			BIT(3)
#define AFE_RTERM_REG			GENMASK(11, 8)

#define PCIE_RX_REG2				0x0054
#define RX_RTERM_SEL			BIT(5)	/* 0: use AFE_RTERM_REG value */

#define PCIE_LTSSM_DIS_ENTRY			0x005c
#define CFG_REFCLK_MODE			GENMASK(9, 8)
#define RFCLK_MODE_DRIVER	0x1
#define OVRD_REFCLK_MODE		BIT(10)	/* 1: use CFG_RFCLK_MODE */

#define PCIE_TX_REG1				0x0064
#define TX_RTERM_REG			GENMASK(15, 12)
#define TX_RTERM_SEL			BIT(25)	/* 1: use TX_RTERM_REG */

/* Zeroed for the combo PHY operating in USB mode */
#define USB3_TEST_CTRL				0x0068

/* PHY calibration values, determined by the combo PHY at probe time */
#define PCIE_RCAL_RESULT			0x0084	/* Port A PHY only */
#define RTERM_VALUE_RX			GENMASK(3, 0)
#define RTERM_VALUE_TX			GENMASK(7, 4)
#define R_TUNE_DONE			BIT(10)

static u32 k1_phy_rterm = ~0;     /* Invalid initial value */

/* Save the RX and TX receiver termination values */
static void k1_phy_rterm_set(u32 val)
{
	k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX);
}

static bool k1_phy_rterm_valid(void)
{
	/* Valid if no bits outside those we care about are set */
	return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX));
}

static u32 k1_phy_rterm_rx(void)
{
	return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm);
}

static u32 k1_phy_rterm_tx(void)
{
	return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm);
}

/* Only the combo PHY has a PMU pointer defined */
static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy)
{
	return !!k1_phy->pmu;
}

/* The PLL clocks are driven by the external oscillator */
static const struct clk_parent_data k1_pcie_phy_data[] = {
	{ .fw_name = "refclk", },
};

static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw)
{
	return container_of(clk_hw, struct k1_pcie_phy, pll_hw);
}

/* USB mode only works on the combo PHY, which has only one lane */
static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy)
{
	void __iomem *regs = k1_phy->regs;
	u32 val;

	val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
	val &= ~CFG_INTERNAL_TIMER_ADJ;
	val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB);
	writel(val, regs + PCIE_PU_ADDR_CLK_CFG);

	val = readl(regs + PCIE_PU_PLL_1);
	val &= ~SSC_DEP_SEL;
	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM);
	writel(val, regs + PCIE_PU_PLL_1);
}

/* Perform PCIe-specific register updates before starting the PLL clock */
static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy)
{
	void __iomem *regs = k1_phy->regs;
	u32 val;
	u32 i;

	for (i = 0; i < k1_phy->pcie_lanes; i++) {
		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
		val &= ~CFG_INTERNAL_TIMER_ADJ;
		val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE);
		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);

		regs += PHY_LANE_OFFSET;	/* Next lane */
	}

	regs = k1_phy->regs;
	val = readl(regs + PCIE_RC_DONE_STATUS);
	val |= CFG_FORCE_RCV_RETRY;
	writel(val, regs + PCIE_RC_DONE_STATUS);

	val = readl(regs + PCIE_PU_PLL_1);
	val &= ~SSC_DEP_SEL;
	val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE);
	writel(val, regs + PCIE_PU_PLL_1);

	val = readl(regs + PCIE_PU_PLL_2);
	val |= GEN_REF100;		/* Enable 100 MHz PLL output clock */
	writel(val, regs + PCIE_PU_PLL_2);
}

static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw)
{
	struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw);
	void __iomem *regs = k1_phy->regs;
	u32 val;
	u32 i;

	if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
		k1_pcie_phy_pll_prepare_usb(k1_phy);
	else
		k1_pcie_phy_pll_prepare_pcie(k1_phy);

	/*
	 * Disable 100 MHz input reference with spread-spectrum
	 * clocking and select the 24 MHz clock input frequency
	 */
	val = readl(regs + PCIE_PU_PLL_1);
	val &= ~REF_100_WSSC;
	val &= ~FREF_SEL;
	val |= FIELD_PREP(FREF_SEL, FREF_24M);
	writel(val, regs + PCIE_PU_PLL_1);

	/* Mark PLL configuration done on all lanes */
	for (i = 0; i < k1_phy->pcie_lanes; i++) {
		val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
		val |= CFG_SW_PHY_INIT_DONE;
		writel(val, regs + PCIE_PU_ADDR_CLK_CFG);

		regs += PHY_LANE_OFFSET;	/* Next lane */
	}

	/*
	 * Wait for indication the PHY PLL is locked.  Lanes for ports
	 * B and C share a PLL, so it's enough to sample just lane 0.
	 */
	return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG,
				  val, val & PLL_READY,
				  POLL_DELAY, PLL_TIMEOUT);
}

/* Prepare implies enable, and once enabled, it's always on */
static const struct clk_ops k1_pcie_phy_pll_ops = {
	.prepare	= k1_pcie_phy_pll_prepare,
};

/* We represent the PHY PLL as a private clock */
static int k1_pcie_phy_pll_setup(