path: root/drivers/pci/controller/pcie-tegra264.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * PCIe host controller driver for Tegra264 SoC
 *
 * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci-ecam.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <soc/tegra/bpmp.h>
#include <soc/tegra/bpmp-abi.h>
#include <soc/tegra/fuse.h>

#include "../pci.h"

/* XAL registers */
#define XAL_RC_ECAM_BASE_HI			0x00
#define XAL_RC_ECAM_BASE_LO			0x04
#define XAL_RC_ECAM_BUSMASK			0x08
#define XAL_RC_IO_BASE_HI			0x0c
#define XAL_RC_IO_BASE_LO			0x10
#define XAL_RC_IO_LIMIT_HI			0x14
#define XAL_RC_IO_LIMIT_LO			0x18
#define XAL_RC_MEM_32BIT_BASE_HI		0x1c
#define XAL_RC_MEM_32BIT_BASE_LO		0x20
#define XAL_RC_MEM_32BIT_LIMIT_HI		0x24
#define XAL_RC_MEM_32BIT_LIMIT_LO		0x28
#define XAL_RC_MEM_64BIT_BASE_HI		0x2c
#define XAL_RC_MEM_64BIT_BASE_LO		0x30
#define XAL_RC_MEM_64BIT_LIMIT_HI		0x34
#define XAL_RC_MEM_64BIT_LIMIT_LO		0x38
#define XAL_RC_BAR_CNTL_STANDARD		0x40
#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN	BIT(0)
#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN	BIT(1)
#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN	BIT(2)

/* XTL registers */
#define XTL_RC_PCIE_CFG_LINK_CAPS		0x56
#define XTL_RC_PCIE_CFG_LINK_STATUS		0x5a

#define XTL_RC_MGMT_PERST_CONTROL		0x218
#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N	BIT(0)

#define XTL_RC_MGMT_CLOCK_CONTROL		0x47c
#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT	BIT(9)

struct tegra264_pcie {
	struct device *dev;

	/* I/O memory */
	void __iomem *xal;
	void __iomem *xtl;
	void __iomem *ecam;

	/* bridge configuration */
	struct pci_config_window *cfg;
	struct pci_host_bridge *bridge;

	/* BPMP and bandwidth management */
	struct icc_path *icc_path;
	struct tegra_bpmp *bpmp;
	u32 ctl_id;

	bool supports_hotplug;
	bool link_up;
};

static void tegra264_pcie_power_off(struct tegra264_pcie *pcie)
{
	struct tegra_bpmp_message msg = {};
	struct mrq_pcie_request req = {};
	int err;

	req.cmd = CMD_PCIE_RP_CONTROLLER_OFF;
	req.rp_ctrlr_off.rp_controller = pcie->ctl_id;

	msg.mrq = MRQ_PCIE;
	msg.tx.data = &req;
	msg.tx.size = sizeof(req);

	err = tegra_bpmp_transfer(pcie->bpmp, &msg);
	if (err)
		dev_err(pcie->dev, "failed to turn off PCIe #%u: %pe\n",
			pcie->ctl_id, ERR_PTR(err));

	if (msg.rx.ret)
		dev_err(pcie->dev, "failed to turn off PCIe #%u: %d\n",
			pcie->ctl_id, msg.rx.ret);
}

static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie)
{
	u32 value, speed, width;
	int err;

	/*
	 * If the link is up, read the negotiated speed and width fields from
	 * the link status register. Otherwise, read the corresponding values
	 * from the link capabilities register to ensure the link works after
	 * hotplug.
	 *
	 * Ideally we'll want to update this dynamically, either on hotplug
	 * or bandwidth change notifications. Neither of those are currently
	 * possible, so this is as good as it gets for now.
	 */
	if (pcie->link_up) {
		value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS);
		speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, value);
		width = FIELD_GET(PCI_EXP_LNKSTA_NLW, value);
	} else {
		value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_CAPS);
		speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, value);
		width = FIELD_GET(PCI_EXP_LNKCAP_MLW, value);
	}

	value = Mbps_to_icc(width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]));

	/*
	 * We don't want to error out here because a boot-critical device
	 * could be connected to this root port. Failure to set the bandwidth
	 * request may have an adverse impact on performance, but it is not
	 * generally fatal, so we opt to continue regardless so that users
	 * get a chance to fix things.
	 */
	err = icc_set_bw(pcie->icc_path, value, value);
	if (err < 0)
		dev_err(pcie->dev,
			"failed to request bandwidth (%u kBps): %pe\n",
			value, ERR_PTR(err));
}

/*
 * The various memory regions used by the controller (I/O, memory, ECAM) are
 * set up during early boot and have hardware-level protections in place. If
 * the DT ranges don't match what's been setup, the controller won't be able
 * to write the address endpoints properly, so make sure to validate that DT
 * and firmware programming agree on these ranges.
 */
static bool tegra264_pcie_valid_ranges(struct platform_device *pdev)
{
	struct tegra264_pcie *pcie = platform_get_drvdata(pdev);
	struct device_node *np = pcie->dev->of_node;
	struct of_pci_range_parser parser;
	phys_addr_t phys, limit, hi, lo;
	struct of_pci_range range;
	struct resource *res;
	bool status = true;
	u32 value;
	int err;

	err = of_pci_range_parser_init(&parser, np);
	if (err < 0)
		return false;

	for_each_of_pci_range(&parser, &range) {
		unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable;
		unsigned long type = range.flags & IORESOURCE_TYPE_BITS;
		phys_addr_t start, end, mask;
		const char *region = NULL;

		end = range.cpu_addr + range.size - 1;
		start = range.cpu_addr;

		switch (type) {
		case IORESOURCE_IO:
			addr_hi = XAL_RC_IO_BASE_HI;
			addr_lo = XAL_RC_IO_BASE_LO;
			limit_hi = XAL_RC_IO_LIMIT_HI;
			limit_lo = XAL_RC_IO_LIMIT_LO;
			enable = XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN;
			mask = SZ_64K - 1;
			region = "I/O";
			break;

		case IORESOURCE_MEM:
			if (range.flags & IORESOURCE_PREFETCH) {
				addr_hi = XAL_RC_MEM_64BIT_BASE_HI;
				addr_lo = XAL_RC_MEM_64BIT_BASE_LO;
				limit_hi = XAL_RC_MEM_64BIT_LIMIT_HI;
				limit_lo = XAL_RC_MEM_64BIT_LIMIT_LO;
				enable = XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN;
				region = "prefetchable memory";
			} else {
				addr_hi = XAL_RC_MEM_32BIT_BASE_HI;
				addr_lo = XAL_RC_MEM_32BIT_BASE_LO;
				limit_hi = XAL_RC_MEM_32BIT_LIMIT_HI;
				limit_lo = XAL_RC_MEM_32BIT_LIMIT_LO;
				enable = XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN;
				region = "memory";
			}

			mask = SZ_1M - 1;
			break;
		}

		/* not interested in anything that's not I/O or memory */
		if (!region)
			continue;

		/* don't check regions that haven't been enabled */
		value = readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD);
		if ((value & enable) == 0)
			continue;

		hi = readl(pcie->xal + addr_hi);
		lo = readl(pcie->xal + addr_lo);
		phys = ((hi << 16) << 16) | lo;

		hi = readl(pcie->xal + limit_hi);
		lo = readl(pcie->xal + limit_lo);
		limit = ((hi << 16) << 16) | lo | mask;

		if (phys != start || limit != end) {
			dev_err(pcie->dev,
				"%s region mismatch: %pap-%pap -> %pap-%pap\n",
				region, &phys, &limit, &start, &end);
			status = false;
		}
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam");
	if (!res)
		return false;

	hi = readl(pcie->xal + XAL_RC_ECAM_BASE_HI);
	lo = readl(pcie->xal + XAL_RC_ECAM_BASE_LO);
	phys = ((hi << 16) << 16) | lo;

	value = readl(pcie->xal + XAL_RC_ECAM_BUSMASK);
	limit = phys + ((value + 1) << 20) - 1;

	if (phys != res->start || limit != res->end) {
		dev_err(pcie->dev,
			"ECAM region mismatch: %pap-%pap -> %pap-%pap\n",
			&phys, &limit, &res->start, &res->end);
		status = false;
	}

	return status;
}

static bool tegra264_pcie_supports_hotplug(struct tegra264_pcie *pcie