path: root/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
 * Copyright (C) 2022 MediaTek Inc.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rtnetlink.h>

#include "mt7996.h"
#include "mac.h"
#include "mcu.h"
#include "../trace.h"
#include "../dma.h"

static bool wed_enable;
module_param(wed_enable, bool, 0644);

static const struct __base mt7996_reg_base[] = {
	[WF_AGG_BASE]		= { { 0x820e2000, 0x820f2000, 0x830e2000 } },
	[WF_ARB_BASE]		= { { 0x820e3000, 0x820f3000, 0x830e3000 } },
	[WF_TMAC_BASE]		= { { 0x820e4000, 0x820f4000, 0x830e4000 } },
	[WF_RMAC_BASE]		= { { 0x820e5000, 0x820f5000, 0x830e5000 } },
	[WF_DMA_BASE]		= { { 0x820e7000, 0x820f7000, 0x830e7000 } },
	[WF_WTBLOFF_BASE]	= { { 0x820e9000, 0x820f9000, 0x830e9000 } },
	[WF_ETBF_BASE]		= { { 0x820ea000, 0x820fa000, 0x830ea000 } },
	[WF_LPON_BASE]		= { { 0x820eb000, 0x820fb000, 0x830eb000 } },
	[WF_MIB_BASE]		= { { 0x820ed000, 0x820fd000, 0x830ed000 } },
	[WF_RATE_BASE]		= { { 0x820ee000, 0x820fe000, 0x830ee000 } },
};

static const u32 mt7996_offs[] = {
	[MIB_RVSR0]		= 0x720,
	[MIB_RVSR1]		= 0x724,
	[MIB_BTSCR5]		= 0x788,
	[MIB_BTSCR6]		= 0x798,
	[MIB_RSCR1]		= 0x7ac,
	[MIB_RSCR27]		= 0x954,
	[MIB_RSCR28]		= 0x958,
	[MIB_RSCR29]		= 0x95c,
	[MIB_RSCR30]		= 0x960,
	[MIB_RSCR31]		= 0x964,
	[MIB_RSCR33]		= 0x96c,
	[MIB_RSCR35]		= 0x974,
	[MIB_RSCR36]		= 0x978,
	[MIB_BSCR0]		= 0x9cc,
	[MIB_BSCR1]		= 0x9d0,
	[MIB_BSCR2]		= 0x9d4,
	[MIB_BSCR3]		= 0x9d8,
	[MIB_BSCR4]		= 0x9dc,
	[MIB_BSCR5]		= 0x9e0,
	[MIB_BSCR6]		= 0x9e4,
	[MIB_BSCR7]		= 0x9e8,
	[MIB_BSCR17]		= 0xa10,
	[MIB_TRDR1]		= 0xa28,
	[HIF_REMAP_L1]		= 0x24,
	[HIF_REMAP_BASE_L1]	= 0x130000,
	[HIF_REMAP_L2]		= 0x1b4,
	[HIF_REMAP_BASE_L2]	= 0x1000,
	[CBTOP1_PHY_END]	= 0x77ffffff,
	[INFRA_MCU_END]		= 0x7c3fffff,
	[WTBLON_WDUCR]		= 0x370,
	[WTBL_UPDATE]		= 0x380,
	[WTBL_ITCR]		= 0x3b0,
	[WTBL_ITCR0]		= 0x3b8,
	[WTBL_ITCR1]		= 0x3bc,
};

static const u32 mt7992_offs[] = {
	[MIB_RVSR0]		= 0x760,
	[MIB_RVSR1]		= 0x764,
	[MIB_BTSCR5]		= 0x7c8,
	[MIB_BTSCR6]		= 0x7d8,
	[MIB_RSCR1]		= 0x7f0,
	[MIB_RSCR27]		= 0x998,
	[MIB_RSCR28]		= 0x99c,
	[MIB_RSCR29]		= 0x9a0,
	[MIB_RSCR30]		= 0x9a4,
	[MIB_RSCR31]		= 0x9a8,
	[MIB_RSCR33]		= 0x9b0,
	[MIB_RSCR35]		= 0x9b8,
	[MIB_RSCR36]		= 0x9bc,
	[MIB_BSCR0]		= 0xac8,
	[MIB_BSCR1]		= 0xacc,
	[MIB_BSCR2]		= 0xad0,
	[MIB_BSCR3]		= 0xad4,
	[MIB_BSCR4]		= 0xad8,
	[MIB_BSCR5]		= 0xadc,
	[MIB_BSCR6]		= 0xae0,
	[MIB_BSCR7]		= 0xae4,
	[MIB_BSCR17]		= 0xb0c,
	[MIB_TRDR1]		= 0xb24,
	[HIF_REMAP_L1]		= 0x8,
	[HIF_REMAP_BASE_L1]	= 0x40000,
	[HIF_REMAP_L2]		= 0x1b4,
	[HIF_REMAP_BASE_L2]	= 0x1000,
	[CBTOP1_PHY_END]	= 0x77ffffff,
	[INFRA_MCU_END]		= 0x7c3fffff,
	[WTBLON_WDUCR]		= 0x370,
	[WTBL_UPDATE]		= 0x380,
	[WTBL_ITCR]		= 0x3b0,
	[WTBL_ITCR0]		= 0x3b8,
	[WTBL_ITCR1]		= 0x3bc,
};

static const u32 mt7990_offs[] = {
	[MIB_RVSR0]		= 0x800,
	[MIB_RVSR1]		= 0x804,
	[MIB_BTSCR5]		= 0x868,
	[MIB_BTSCR6]		= 0x878,
	[MIB_RSCR1]		= 0x890,
	[MIB_RSCR27]<