path: root/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c

// SPDX-License-Identifier: BSD-3-Clause-Clear
/* Copyright (C) 2020 MediaTek Inc. */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtnetlink.h>
#include <linux/pci.h>

#include "mt7915.h"
#include "mac.h"
#include "mcu.h"
#include "../trace.h"
#include "../dma.h"

static bool wed_enable;
module_param(wed_enable, bool, 0644);
MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support");

static const u32 mt7915_reg[] = {
	[INT_SOURCE_CSR]		= 0xd7010,
	[INT_MASK_CSR]			= 0xd7014,
	[INT1_SOURCE_CSR]		= 0xd7088,
	[INT1_MASK_CSR]			= 0xd708c,
	[INT_MCU_CMD_SOURCE]		= 0xd51f0,
	[INT_MCU_CMD_EVENT]		= 0x3108,
	[WFDMA0_ADDR]			= 0xd4000,
	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
	[CBTOP1_PHY_END]		= 0x77ffffff,
	[INFRA_MCU_ADDR_END]		= 0x7c3fffff,
	[FW_ASSERT_STAT_ADDR]		= 0x219848,
	[FW_EXCEPT_TYPE_ADDR]		= 0x21987c,
	[FW_EXCEPT_COUNT_ADDR]		= 0x219848,
	[FW_CIRQ_COUNT_ADDR]		= 0x216f94,
	[FW_CIRQ_IDX_ADDR]		= 0x216ef8,
	[FW_CIRQ_LISR_ADDR]		= 0x2170ac,
	[FW_TASK_ID_ADDR]		= 0x216f90,
	[FW_TASK_IDX_ADDR]		= 0x216f9c,
	[FW_TASK_QID1_ADDR]		= 0x219680,
	[FW_TASK_QID2_ADDR]		= 0x219760,
	[FW_TASK_START_ADDR]		= 0x219558,
	[FW_TASK_END_ADDR]		= 0x219554,
	[FW_TASK_SIZE_ADDR]		= 0x219560,
	[FW_LAST_MSG_ID_ADDR]		= 0x216f70,
	[FW_EINT_INFO_ADDR]		= 0x219818,
	[FW_SCHED_INFO_ADDR]		= 0x219828,
	[SWDEF_BASE_ADDR]		= 0x41f200,
	[TXQ_WED_RING_BASE]		= 0xd7300,
	[RXQ_WED_RING_BASE]		= 0xd7410,
	[RXQ_WED_DATA_RING_BASE]	= 0xd4500,
};

static const u32 mt7916_reg[] = {
	[INT_SOURCE_CSR]		= 0xd4200,
	[INT_MASK_CSR]			= 0xd4204,
	[INT1_SOURCE_CSR]		= 0xd8200,
	[INT1_MASK_CSR]			= 0xd8204,
	[INT_MCU_CMD_SOURCE]		= 0xd41f0,
	[INT_MCU_CMD_EVENT]		= 0x2108,
	[WFDMA0_ADDR]			= 0xd4000,
	[WFDMA0_PCIE1_ADDR]		= 0xd8000,
	[WFDMA_EXT_CSR_ADDR]		= 0xd7000,
	[CBTOP1_PHY_END]		= 0x7fffffff,
	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
	[FW_ASSERT_STAT_ADDR]		= 0x02204c14,
	[FW_EXCEPT_TYPE_ADDR]		= 0x022051a4,
	[FW_EXCEPT_COUNT_ADDR]		= 0x022050bc,
	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
	[FW_CIRQ_IDX_ADDR]		= 0x02204f84,
	[FW_CIRQ_LISR_ADDR]		= 0x022050d0,
	[FW_TASK_ID_ADDR]		= 0x0220406c,
	[FW_TASK_IDX_ADDR]		= 0x0220500c,
	[FW_TASK_QID1_ADDR]		= 0x022028c8,
	[FW_TASK_QID2_ADDR]		= 0x02202a38,
	[FW_TASK_START_ADDR]		= 0x0220286c,
	[FW_TASK_END_ADDR]		= 0x02202870,
	[FW_TASK_SIZE_ADDR]		= 0x02202878,
	[FW_LAST_MSG_ID_ADDR]		= 0x02204fe8,
	[FW_EINT_INFO_ADDR]		= 0x0220525c,
	[FW_SCHED_INFO_ADDR]		= 0x0220516c,
	[SWDEF_BASE_ADDR]		= 0x411400,
	[TXQ_WED_RING_BASE]		= 0xd7300,
	[RXQ_WED_RING_BASE]		= 0xd7410,
	[RXQ_WED_DATA_RING_BASE]	= 0xd4540,
};

static const u32 mt7986_reg[] = {
	[INT_SOURCE_CSR]		= 0x24200,
	[INT_MASK_CSR]			= 0x24204,
	[INT1_SOURCE_CSR]		= 0x28200,
	[INT1_MASK_CSR]			= 0x28204,
	[INT_MCU_CMD_SOURCE]		= 0x241f0,
	[INT_MCU_CMD_EVENT]		= 0x54000108,
	[WFDMA0_ADDR]			= 0x24000,
	[WFDMA0_PCIE1_ADDR]		= 0x28000,
	[WFDMA_EXT_CSR_ADDR]		= 0x27000,
	[CBTOP1_PHY_END]		= 0x7fffffff,
	[INFRA_MCU_ADDR_END]		= 0x7c085fff,
	[FW_ASSERT_STAT_ADDR]		= 0x02204b54,
	[FW_EXCEPT_TYPE_ADDR]		= 0x022050dc,
	[FW_EXCEPT_COUNT_ADDR]		= 0x02204ffc,
	[FW_CIRQ_COUNT_ADDR]		= 0x022001ac,
	[FW_CIRQ_IDX_ADDR]		= 0x02204ec4,
	[FW_CIRQ_LISR_ADDR]		=