path: root/drivers/net/wireless/ath/ath12k/mhi.c

// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#include <linux/msi.h>
#include <linux/pci.h>
#include <linux/firmware.h>

#include "core.h"
#include "debug.h"
#include "mhi.h"
#include "pci.h"

#define MHI_TIMEOUT_DEFAULT_MS	90000
#define OTP_INVALID_BOARD_ID	0xFFFF
#define OTP_VALID_DUALMAC_BOARD_ID_MASK		0x1000
#define MHI_CB_INVALID	0xff

void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab)
{
	u32 val;

	val = ath12k_pci_read32(ab, MHISTATUS);

	ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val);

	/* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS
	 * has SYSERR bit set and thus need to set MHICTRL_RESET
	 * to clear SYSERR.
	 */
	ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);

	mdelay(10);
}

static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab)
{
	ath12k_pci_write32(ab, PCIE_TXVECDB, 0);
}

static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab)
{
	ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0);
}

static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab)
{
	ath12k_pci_write32(ab, PCIE_RXVECDB, 0);
}

static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab)
{
	ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0);
}

void ath12k_mhi_clear_vector(struct ath12k_base *ab)
{
	ath12k_mhi_reset_txvecdb(ab);
	ath12k_mhi_reset_txvecstatus(ab);
	ath12k_mhi_reset_rxvecdb(ab);
	ath12k_mhi_reset_rxvecstatus(ab);
}

static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)
{
	struct ath12k_base *ab = ab_pci->ab;
	u32 user_base_data, base_vector;
	int ret, num_vectors, i;
	int *irq;
	unsigned int msi_data;

	ret = ath12k_pci_get_user_msi_assignment(ab,
						 "MHI", &num_vectors,
						 &user_base_data, &base_vector);
	if (ret)
		return ret;

	ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
		   num_vectors, base_vector);

	irq = kzalloc_objs(*irq, num_vectors);
	if (!irq)
		return -ENOMEM;

	msi_data = base_vector;
	for (i = 0; i < num_vectors; i++) {
		if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
			irq[i] = ath12k_pci_get_msi_irq(ab->dev,
							msi_data++);
		else
			irq[i] = ath12k_pci_get_msi_irq(ab->dev,
							msi_data);
	}

	ab_pci->mhi_ctrl->irq = irq;
	ab_pci->mhi_ctrl->nr_irqs = num_vectors;

	return 0;
}

static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
{
	return 0;
}

static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
{
}

static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason)
{
	switch (reason) {
	case MHI_CB_IDLE:
		return "MHI_CB_IDLE";
	case MHI_CB_PENDING_DATA:
		return "MHI_CB_PENDING_DATA";
	case MHI_CB_LPM_ENTER:
		return "MHI_CB_LPM_ENTER";
	case MHI_CB_LPM_EXIT:
		return "MHI_CB_LPM_EXIT";
	case MHI_CB_EE_RDDM:
		return "MHI_CB_EE_RDDM";
	case MHI_CB_EE_MISSION_MODE:
		return "MHI_CB_EE_MISSION_MODE";
	case MHI_CB_SYS_ERROR:
		return "MHI_CB_SYS_ERROR";
	case MHI_CB_FATAL_ERROR:
		return "MHI_CB_FATAL_ERROR";
	case MHI_CB_BW_REQ:
		return "MHI_CB_BW_REQ";
	default:
		return "UNKNOWN";
	}
}

static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
				    enum mhi_callback cb)
{
	struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);

	ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n",
		   ath12k_mhi_op_callback_to_str(cb));

	switch (cb) {
	case MHI_CB_SYS_ERROR:
		ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
		break;
	case MHI_CB_EE_RDDM:
		if (ab_pci->mhi_pre_cb == MHI_CB_EE_RDDM) {
			ath12k_dbg(ab, ATH12K_DBG_BOOT,
				   "do not queue again for consecutive RDDM event\n");
			break;
		}

		if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) {
			set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags);
			set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags);
			queue_work(ab->workqueue_aux, &ab->reset_work);
		}
		break;
	default:
		break;
	}

	ab_pci->mhi_pre_cb = cb;
}

static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
				  void __iomem *addr,
				  u32 *out)
{
	*out = readl(addr);

	return 0;
}

static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
				    void __iomem *addr,
				    u32 val)
{
	writel(val, addr);
}

int ath12k_mhi_register(struct ath12k_pci *ab_pci)
{
	struct ath12k_base *ab = ab_pci->ab;
	struct mhi_controller *mhi_ctrl;
	unsigned int board_id;
	int ret;
	bool dualmac = false;

	mhi_ctrl = mhi_alloc_controller();
	if (!mhi_ctrl)
		return -ENOMEM;

	ab_pci->mhi_pre_cb = MHI_CB_INVALID;
	ab_pci->mhi_ctrl = mhi_ctrl;
	mhi_ctrl->cntrl_dev = ab->dev;
	mhi_ctrl->regs = ab->mem;
	mhi_ctrl->reg_len = ab->mem_len;
	mhi_ctrl->rddm_size = ab->hw_params->rddm_size;

	if (ab->hw_params->otp_board_id_register) {
		board_id =
			ath12k_pci_read32(ab, ab->hw_params->otp_board_id_register);
		board_id = u32_get_bits(board_id, OTP_BOARD_ID_MASK);

		if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) {
			ath12k_dbg(ab, ATH12K_DBG_BOOT,
				   "failed to read board id\n");
		} else if (board_id & OTP_VALID_DUALMAC_BOARD_ID_MASK) {
			dualmac = true;
			ath12k_dbg(ab, ATH12K_DBG_BOOT,
				   "dualmac fw selected for board id: %x\n", board_id);
		}
	}

	if (dualmac) {
		if (ab->fw.amss_dualmac_data && ab->fw.amss_dualmac_len > 0) {
			/* use MHI firmware file from firmware-N.bin */
			mhi_ctrl->fw_data = ab->fw.amss_dualmac_data;
			mhi_ctrl->fw_sz = ab->fw.amss_dualmac_len;
		} else {
			ath12k_warn(ab, "dualmac firmware IE not present in firmware-N.bin\n");
			ret = -ENOENT;
			goto free_controller;
		}
	} else {
		if (ab->fw.amss_data && ab->fw.amss_len > 0) {
			/* use MHI firmware file from firmware-N.bin */
			mhi_ctrl->fw_data = ab->fw.amss_data;
			mhi_ctrl->fw_sz = ab->fw.amss_len;
		} else {
			/* use the old separate mhi.bin MHI firmware file */
			ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE,
							 ab_pci->amss_path,
							 sizeof(ab_pci->amss_path));
			mhi_ctrl->fw_image = ab_pci->amss_path;
		}