// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/dma-mapping.h>
#include "debug.h"
#include "hif.h"
static void ath12k_hal_ce_dst_setup(struct ath12k_base *ab,
struct hal_srng *srng, int ring_num)
{
ab->hal.ops->ce_dst_setup(ab, srng, ring_num);
}
static void ath12k_hal_srng_src_hw_init(struct ath12k_base *ab,
struct hal_srng *srng)
{
ab->hal.ops->srng_src_hw_init(ab, srng);
}
static void ath12k_hal_srng_dst_hw_init(struct ath12k_base *ab,
struct hal_srng *srng)
{
ab->hal.ops->srng_dst_hw_init(ab, srng);
}
static void ath12k_hal_set_umac_srng_ptr_addr(struct ath12k_base *ab,
struct hal_srng *srng)
{
ab->hal.ops->set_umac_srng_ptr_addr(ab, srng);
}
static int ath12k_hal_srng_get_ring_id(struct ath12k_hal *hal,
enum hal_ring_type type,
int ring_num, int mac_id)
{
return hal->ops->srng_get_ring_id(hal, type, ring_num, mac_id);
}
int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab,
enum hal_ring_type ring_type,
int ring_num)
{
return ab->hal.ops->srng_update_shadow_config(ab, ring_type,
ring_num);
}
u32 ath12k_hal_ce_get_desc_size(struct ath12k_hal *hal, enum hal_ce_desc type)
{
return hal->ops->ce_get_desc_size(type);
}
void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id)
{
ab->hal.ops->tx_set_dscp_tid_map(ab, id);
}
void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab,
u32 bank_config, u8 bank_id)
{
ab->hal.ops->tx_configure_bank_register(ab, bank_config, bank_id);
}
void ath12k_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab)
{
ab->hal.ops->reoq_lut_addr_read_enable(ab);
}
void ath12k_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab)
{
ab->hal.ops->reoq_lut_set_max_peerid(ab);
}
void ath12k_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr)
{
ab->hal.ops->write_ml_reoq_lut_addr(ab, paddr);
}
void ath12k_hal_write_reoq_lut_addr(struct ath12k_base *ab, dma_addr_t paddr)
{
ab->hal.ops->write_reoq_lut_addr(ab, paddr);
}
void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
struct hal_wbm_idle_scatter_list *sbuf,
u32 nsbufs, u32 tot_link_desc,
u32 end_offset)
{
ab->hal.ops->setup_link_idle_list(ab, sbuf, nsbufs, tot_link_desc,
end_offset);
}
void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map)
{
ab->hal.ops->reo_hw_setup(ab, ring_hash_map);
}
void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, struct hal_srng *srng)
{
ab->hal.ops->reo_init_cmd_ring(ab, srng);
}
void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab)
{
ab->hal.ops->reo_shared_qaddr_cache_clear(ab);
}
EXPORT_SYMBOL(ath12k_hal_reo_shared_qaddr_cache_clear);
void ath12k_hal_rx_buf_addr_info_set(struct ath12k_hal *hal,
struct ath12k_buffer_addr *binfo,
dma_addr_t paddr, u32 cookie, u8 manager)
{
hal->ops->rx_buf_addr_info_set(binfo, paddr, cookie, manager);
}
void ath12k_hal_rx_buf_addr_info_get(struct ath12k_hal *hal,
struct ath12k_buffer_addr *binfo,
dma_addr_t *paddr, u32 *msdu_cookies,
u8 *rbm)
{
hal->ops->rx_buf_addr_info_get(binfo, paddr, msdu_cookies, rbm);
}
void ath12k_hal_rx_msdu_list_get(struct ath12k_hal *hal, struct ath12k *ar,
void *link_desc,
void *msdu_list,
u16 *num_msdus)
{
hal->ops->rx_msdu_list_get(ar, link_desc, msdu_list, num_msdus);
}
void ath12k_hal_rx_reo_ent_buf_paddr_get(struct ath12k_hal *hal, void *rx_desc,
dma_addr_t *paddr,
u32 *sw_cookie,
struct ath12k_buffer_addr **pp_buf_addr,
u8 *rbm, u32 *msdu_cnt)
{
hal->ops->rx_reo_ent_buf_paddr_get(rx_desc, paddr, sw_cookie,
pp_buf_addr, rbm, msdu_cnt);
}
void ath12k_hal_cc_config(struct ath12k_base *ab)
{
ab->hal.ops->cc_config(ab);
}
enum hal_rx_buf_return_buf_manager
ath12k_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id)
{
return hal->ops->get_idle_link_rbm(hal, device_id);
}
static int ath12k_hal_alloc_cont_rdp(struct ath12k_hal *hal)
{
size_t size;
size = sizeof(u32)