path: root/drivers/net/phy/microchip_rds_ptp.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2024 Microchip Technology

#include "microchip_rds_ptp.h"

static int mchp_rds_phy_read_mmd(struct mchp_rds_ptp_clock *clock,
				 u32 offset, enum mchp_rds_ptp_base base)
{
	struct phy_device *phydev = clock->phydev;
	u32 addr;

	addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
			  BASE_CLK(clock)));

	return phy_read_mmd(phydev, PTP_MMD(clock), addr);
}

static int mchp_rds_phy_write_mmd(struct mchp_rds_ptp_clock *clock,
				  u32 offset, enum mchp_rds_ptp_base base,
				  u16 val)
{
	struct phy_device *phydev = clock->phydev;
	u32 addr;

	addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
			  BASE_CLK(clock)));

	return phy_write_mmd(phydev, PTP_MMD(clock), addr, val);
}

static int mchp_rds_phy_modify_mmd(struct mchp_rds_ptp_clock *clock,
				   u32 offset, enum mchp_rds_ptp_base base,
				   u16 mask, u16 val)
{
	struct phy_device *phydev = clock->phydev;
	u32 addr;

	addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
			  BASE_CLK(clock)));

	return phy_modify_mmd(phydev, PTP_MMD(clock), addr, mask, val);
}

static int mchp_rds_phy_set_bits_mmd(struct mchp_rds_ptp_clock *clock,
				     u32 offset, enum mchp_rds_ptp_base base,
				     u16 val)
{
	struct phy_device *phydev = clock->phydev;
	u32 addr;

	addr = (offset + ((base == MCHP_RDS_PTP_PORT) ? BASE_PORT(clock) :
			  BASE_CLK(clock)));

	return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val);
}

static int