path: root/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.00  has been used for developing this code.
 *
 * This only implements the mac core functions for this chip.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/crc32.h>
#include <linux/slab.h>
#include <linux/ethtool.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include "stmmac.h"
#include "stmmac_fpe.h"
#include "stmmac_pcs.h"
#include "stmmac_vlan.h"
#include "dwmac4.h"
#include "dwmac5.h"

static const struct stmmac_pcs_info dwmac4_pcs_info = {
	.pcs_offset = GMAC_PCS_BASE,
	.rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS,
	.rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
	.int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
};

static int dwmac4_pcs_init(struct stmmac_priv *priv)
{
	if (!priv->dma_cap.pcs)
		return 0;

	return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info);
}

static void dwmac4_core_init(struct mac_device_info *hw,
			     struct net_device *dev)
{
	struct stmmac_priv *priv = netdev_priv(dev);
	void __iomem *ioaddr = hw->pcsr;
	unsigned long clk_rate;
	u32 value;

	value = readl(ioaddr + GMAC_CONFIG);
	writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG);

	/* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
	clk_rate = clk_get_rate(priv->plat->stmmac_clk);
	writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);

	/* Enable GMAC interrupts */
	writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN);

	if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
		init_waitqueue_head(&priv->tstamp_busy_wait);
}

static void dwmac4_irq_modify(struct mac_device_info *hw, u32 disable,
			      u32 enable)
{
	void __iomem *int_mask = hw->pcsr + GMAC_INT_EN;
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&hw->irq_ctrl_lock, flags);
	value = readl(int_mask) & ~disable;
	value |= enable;
	writel(value, int_mask);
	spin_unlock_irqrestore(&hw->irq_ctrl_lock, flags);
}

static void dwmac4_update_caps(struct stmmac_priv *priv)
{
	if (priv->plat->tx_queues_to_use > 1)
		priv->hw->link.caps &= ~(MAC_10HD | MAC_100HD | MAC_1000HD);
	else
		priv->hw->link.caps |= (MAC_10HD | MAC_100HD | MAC_1000HD);
}

static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
				   u8 mode, u32 queue)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);

	value &= GMAC_RX_QUEUE_CLEAR(queue);
	if (mode == MTL_QUEUE_AVB)
		value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
	else if (mode == MTL_QUEUE_DCB)
		value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);

	writel(value, ioaddr + GMAC_RXQ_CTRL0);
}

static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
				     u32 prio, u32 queue)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 clear_mask = 0;
	u32 ctrl2, ctrl3;
	int i;

	ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
	ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);

	/* The software must ensure that the same priority
	 * is not mapped to multiple Rx queues
	 */
	for (i = 0; i < 4; i++)
		clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
						GMAC_RXQCTRL_PSRQX_MASK(i));

	ctrl2 &= ~clear_mask;
	ctrl3