path: root/drivers/net/ethernet/broadcom/bnge/bnge_netdev.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2025 Broadcom */

#ifndef _BNGE_NETDEV_H_
#define _BNGE_NETDEV_H_

#include <linux/bnge/hsi.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/refcount.h>
#include <linux/u64_stats_sync.h>
#include <net/netdev_queues.h>
#include "bnge_db.h"
#include "bnge_hw_def.h"
#include "bnge_link.h"

struct tx_bd {
	__le32 tx_bd_len_flags_type;
	#define TX_BD_TYPE					(0x3f << 0)
	#define TX_BD_TYPE_SHORT_TX_BD				(0x00 << 0)
	#define TX_BD_TYPE_LONG_TX_BD				(0x10 << 0)
	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
	#define TX_BD_FLAGS_BD_CNT_SHIFT			8
	#define TX_BD_FLAGS_LHINT				(3 << 13)
	#define TX_BD_FLAGS_LHINT_SHIFT				13
	#define TX_BD_FLAGS_LHINT_512_AND_SMALLER		(0 << 13)
	#define TX_BD_FLAGS_LHINT_512_TO_1023			(1 << 13)
	#define TX_BD_FLAGS_LHINT_1024_TO_2047			(2 << 13)
	#define TX_BD_FLAGS_LHINT_2048_AND_LARGER		(3 << 13)
	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
	#define TX_BD_LEN					(0xffff << 16)
	#define TX_BD_LEN_SHIFT					16
	u32 tx_bd_opaque;
	__le64 tx_bd_haddr;
} __packed;

struct rx_bd {
	__le32 rx_bd_len_flags_type;
	#define RX_BD_TYPE					(0x3f << 0)
	#define RX_BD_TYPE_RX_PACKET_BD				0x4
	#define RX_BD_TYPE_RX_BUFFER_BD				0x5
	#define RX_BD_TYPE_RX_AGG_BD				0x6
	#define RX_BD_TYPE_16B_BD_SIZE				(0 << 4)
	#define RX_BD_TYPE_32B_BD_SIZE				(1 << 4)
	#define RX_BD_TYPE_48B_BD_SIZE				(2 << 4)
	#define RX_BD_TYPE_64B_BD_SIZE				(3 << 4)
	#define RX_BD_FLAGS_SOP					(1 << 6)
	#define RX_BD_FLAGS_EOP					(1 << 7)
	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
	#define RX_BD_FLAGS_1_BUFFER_PACKET			(0 << 8)
	#define RX_BD_FLAGS_2_BUFFER_PACKET			(1 << 8)
	#define RX_BD_FLAGS_3_BUFFER_PACKET			(2 << 8)
	#define RX_BD_FLAGS_4_BUFFER_PACKET			(3 << 8)
	#define RX_BD_LEN					(0xffff << 16)
	#define RX_BD_LEN_SHIFT					16
	u32 rx_bd_opaque;
	__le64 rx_bd_haddr;
};

struct tx_cmp {
	__le32 tx_cmp_flags_type;
	#define CMP_TYPE					(0x3f << 0)
	#define CMP_TYPE_TX_L2_CMP				0
	#define CMP_TYPE_TX_L2_COAL_CMP				2
	#define CMP_TYPE_TX_L2_PKT_TS_CMP			4
	#define CMP_TYPE_RX_L2_CMP				17
	#define CMP_TYPE_RX_AGG_CMP				18
	#define CMP_TYPE_RX_L2_TPA_START_CMP			19
	#define CMP_TYPE_RX_L2_TPA_END_CMP			21
	#define CMP_TYPE_RX_TPA_AGG_CMP				22
	#define CMP_TYPE_RX_L2_V3_CMP				23
	#define CMP_TYPE_RX_L2_TPA_START_V3_CMP			25
	#define CMP_TYPE_STATUS_CMP				32
	#define CMP_TYPE_REMOTE_DRIVER_REQ			34
	#define CMP_TYPE_REMOTE_DRIVER_RESP			36
	#define CMP_TYPE_ERROR_STATUS				48
	#define CMPL_BASE_TYPE_STAT_EJECT			0x1aUL
	#define CMPL_BASE_TYPE_HWRM_DONE			0x20UL
	#define CMPL_BASE_TYPE_HWRM_FWD_REQ			0x22UL
	#define CMPL_BASE_TYPE_HWRM_FWD_RESP			0x24UL
	#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT			0x2eUL
	#define CMPL_BA_TY_HWRM_ASY_EVT	CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
	#define TX_CMP_FLAGS_ERROR				(1 << 6)
	#define TX_CMP_FLAGS_PUSH				(1 << 7)
	u32 tx_cmp_opaque;
	__le32 tx_cmp_errors_v;
	#define TX_CMP_V					(1 << 0)
	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
	#define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		0
	#define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		2
	#define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG		4
	#define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		5
	#define TX_CMP_ERRORS_ZERO_LENGTH_PKT			(1 << 4)
	#define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			(1 << 5)
	#define TX_CMP_ERRORS_DMA_ERROR				(1 << 6)
	#define TX_CMP_ERRORS_HINT_TOO_SHORT			(1 << 7)
	__le32 sq_cons_idx;
	#define TX_CMP_SQ_CONS_IDX_MASK				0x00ffffff
};

struct bnge_sw_tx_bd {
	struct sk_buff		*skb;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	DEFINE_DMA_UNMAP_LEN(len);
	struct page		*page;
	u8			is_ts_pkt;
	u8			is_push;
	u8			action;
	unsigned short		nr_frags;
	union {
		u16		rx_prod;
		u16		txts_prod;
	};
};

struct bnge_sw_rx_bd {
	void			*data;
	u8			*data_ptr;
	dma_addr_t		mapping;
};

struct bnge_sw_rx_agg_bd {
	netmem_ref		netmem;
	unsigned int		offset;
	dma_addr_t		mapping;
};

#define HWRM_RING_ALLOC_TX	0x1
#define HWRM_RING_ALLOC_RX	0x2
#define HWRM_RING_ALLOC_AGG	0x4
#define HWRM_RING_ALLOC_CMPL	0x8
#define HWRM_RING_ALLOC_NQ	0x10

struct bnge_ring_grp_info {
	u16	fw_stats_ctx;
	u16	fw_grp_id;
	u16	rx_fw_ring_id;
	u16	agg_fw_ring_id;
	u16	nq_fw_ring_id;
};

#define BNGE_DEFAULT_RX_COPYBREAK	256
#define BNGE_MAX_RX_COPYBREAK		1024

#define BNGE_HW_FEATURE_VLAN_ALL_RX	\
		(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
#define BNGE_HW_FEATURE_VLAN_ALL_TX	\
		(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)

enum {
	BNGE_NET_EN_GRO		= BIT(0),
	BNGE_NET_EN_LRO		= BIT(1),
	BNGE_NET_EN_JUMBO	= BIT(2),
};

#define BNGE_NET_EN_TPA		(BNGE_NET_EN_GRO | BNGE_NET_EN_LRO)

#define BNGE_NO_FW_ACCESS(bd)	(pci_channel_offline((bd)->pdev))

#define MAX_TPA		256
#define MAX_TPA_MASK	(MAX_TPA - 1)
#define MAX_TPA_SEGS	0x3f

#define BNGE_TPA_INNER_L3_OFF(hdr_info)	\
	(((hdr_info) >> 18) & 0x1ff)

#define BNGE_TPA_INNER_L2_OFF(hdr_info)	\
	(((hdr_info) >> 9) & 0x1ff)

#define BNGE_TPA_OUTER_L3_OFF(hdr_info)	\
	((hdr_info) & 0x1ff)

struct bnge_tpa_idx_map {
	u16		agg_id_tbl[1024];
	DECLARE_BITMAP(agg_idx_bmap, MAX_TPA);
};

struct bnge_tpa_info {
	void			*data;
	u8			*data_ptr;
	dma_addr_t		mapping;
	u16			len;
	unsigned short		gso_type;
	u32			flags2;
	u32			metadata;
	enum pkt_hash_types	hash_type;
	u32			rss_hash;
	u32			hdr_info;

	u16			cfa_code; /* cfa_code in TPA start compl */
	u8			agg_count;
	bool			vlan_valid;
	bool			cfa_code_valid;
	struct rx_agg_cmp	*agg_arr;
};

/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
 * BD because the first TX BD is always a long BD.
 */
#define BNGE_MIN_TX_DESC_CNT	(MAX_SKB_FRAGS + 2)

#define RX_RING(bn, x)	(((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
#define RX_AGG_RING(bn, x)	(((x) & (bn)->rx_agg_ring_mask) >>	\
				 (BNGE_PAGE_SHIFT - 4))
#define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))

#define TX_RING(bn, x)	(((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
#define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))

#define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4))
#define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))

#define RING_RX(bn, idx)	((idx) & (bn)->rx_ring_mask)
#define NEXT_RX(idx)		((idx) + 1)

#define RING_RX_AGG(bn, idx)	((idx) & (bn)->rx_agg_ring_mask)
#define NEXT_RX_AGG(idx)	((idx) + 1)

#define BNGE_NQ_HDL_IDX_MASK	0x00ffffff
#define BNGE_NQ_HDL_TYPE_MASK	0xff000000
#define BNGE_NQ_HDL_TYPE_SHIFT	24
#define BNGE_NQ_HDL_TYPE_RX	0x00
#define BNGE_NQ_HDL_TYPE_TX	0x01

#define BNGE_NQ_HDL_IDX(hdl)	((hdl) & BNGE_NQ_HDL_IDX_MASK)
#define BNGE_NQ_HDL_TYPE(hdl)	(((hdl) & BNGE_NQ_HDL_TYPE_MASK) >>	\
				 BNGE_NQ_HDL_TYPE_SHIFT)
#define BNGE_GET_RING_STATS64(sw, counter)		\
	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))

#define BNGE_GET_RX_PORT_STATS64(sw, counter)		\
	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))

#define BNGE_GET_TX_PORT_STATS64(sw, counter)		\
	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))

#define BNGE_PORT_STATS_SIZE				\
	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)

#define BNGE_TX_PORT_STATS_BYTE_OFFSET			\
	(sizeof(struct rx_port_stats) + 512)

#define BNGE_RX_STATS_OFFSET(counter)			\
	(offsetof(struct rx_port_stats, counter) / 8)

#define BNGE_TX_STATS_OFFSET(counter)			\
	((offsetof(struct tx_port_stats, counter) +	\
	  BNGE_TX_PORT_STATS_BYTE_OFFSET) / 8)

#define BNGE_RX_STATS_EXT_OFFSET(counter)		\
	(offsetof(struct rx_port_stats_ext, counter) / 8)

#define BNGE_TX_STATS_EXT_OFFSET(counter)		\
	(offsetof(struct tx_port_stats_ext, counter) / 8)

struct bnge_stats_mem {
	u64		*sw_stats;
	u64		*hw_masks;
	void		*hw_stats;
	dma_addr_t	hw_stats_map;
	u32		len;
	struct u64_stats_sync	syncp;
};

enum bnge_net_state {
	BNGE_STATE_NAPI_DISABLED,
	BNGE_STATE_STATS_ENABLE,
};

#define BNGE_TIMER_INTERVAL	HZ

enum bnge_net_flag {
	BNGE_FLAG_PORT_STATS		= BIT(0),
	BNGE_FLAG_PORT_STATS_EXT	= BIT(1),
};

enum bnge_sp_event {
	BNGE_LINK_CHNG_SP_EVENT,
	BNGE_LINK_SPEED_CHNG_SP_EVENT,
	BNGE_LINK_CFG_CHANGE_SP_EVENT,
	BNGE_UPDATE_PHY_SP_EVENT,
	BNGE_PERIODIC_STATS_SP_EVENT,
};

struct bnge_net {
	struct bnge_dev		*bd;
	struct net_device	*netdev;

	u32			priv_flags;

	u32			rx_ring_size;
	u32			rx_buf_size;
	u32			rx_buf_use_size; /* usable size */
	u32			rx_agg_ring_size;
	u32			rx_copybreak;
	u32			rx_ring_mask;
	u32			rx_agg_ring_mask;
	u16			rx_nr_pages;
	u16			rx_agg_nr_pages;

	u32			tx_ring_size;
	u32			tx_ring_mask;
	u16			tx_nr_pages;

	/* NQs and Completion rings */
	u32			cp_ring_size;
	u32			cp_ring_mask;
	u32			cp_bit;
	u16			cp_nr_pages;

#define BNGE_L2_FLTR_HASH_SIZE	32
#define BNGE_L2_FLTR_HASH_MASK	(BNGE_L2_FLTR_HASH_SIZE - 1)
	struct hlist_head	l2_fltr_hash_tbl[BNGE_L2_FLTR_HASH_SIZE];
	u32			hash_seed;
	u64			toeplitz_prefix;

	struct bnge_napi		**bnapi;

	struct bnge_rx_ring_info	*rx_ring;
	struct bnge_tx_ring_info	*tx_ring;

	u16				*tx_ring_map;
	enum dma_data_direction		rx_dir;

	/* grp_info indexed by napi/nq index */
	struct bnge_ring_grp_info	*grp_info;
	struct bnge_vnic_info		*vnic_info;
	int				nr_vnics;
	int				total_irqs;

	u32			tx_wake_thresh;
	u16			rx_offset;
	u16			rx_dma_offset;

	u8			rss_hash_key[HW_HASH_KEY_SIZE];
	u8			rss_hash_key_valid:1;
	u8			rss_hash_key_updated:1;
	int			rsscos_nr_ctxs;
	u32			stats_coal_ticks;

	unsigned long		state;

	u32			msg_enable;
	u16			max_tpa;
	__be16			vxlan_port;
	__be16			nge_port;
	__be16			vxlan_gpe_port;

	unsigned int		current_interval;
	struct timer_list	timer;
	struct workqueue_struct *bnge_pf_wq;
	struct work_struct	sp_task;
	unsigned long		sp_event;

	struct bnge_ethtool_link_info	eth_link_info;

	u64			flags;

	struct bnge_stats_mem	port_stats;
	struct bnge_stats_mem	rx_port_stats_ext;
	struct bnge_stats_mem	tx_port_stats_ext;
	u16			fw_rx_stats_ext_size