path: root/drivers/mmc/host/sdhci-brcmstb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
 *
 * Copyright (C) 2015 Broadcom Corporation
 */

#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mmc/host.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/delay.h>

#include "sdhci-cqhci.h"
#include "sdhci-pltfm.h"
#include "cqhci.h"

#define SDHCI_VENDOR 0x78
#define  SDHCI_VENDOR_ENHANCED_STRB 0x1
#define  SDHCI_VENDOR_GATE_SDCLK_EN 0x2

#define BRCMSTB_MATCH_FLAGS_NO_64BIT		BIT(0)
#define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT	BIT(1)
#define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE	BIT(2)
#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY	BIT(4)

#define BRCMSTB_PRIV_FLAGS_HAS_CQE		BIT(0)
#define BRCMSTB_PRIV_FLAGS_GATE_CLOCK		BIT(1)

#define SDHCI_ARASAN_CQE_BASE_ADDR		0x200

#define SDIO_CFG_CTRL				0x0
#define SDIO_CFG_CTRL_SDCD_N_TEST_EN		BIT(31)
#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV		BIT(30)
#define SDIO_CFG_OP_DLY				0x34
#define SDIO_CFG_OP_DLY_DEFAULT			0x80000003
#define SDIO_CFG_CQ_CAPABILITY			0x4c
#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
#define SDIO_CFG_SD_PIN_SEL			0x44
#define SDIO_CFG_V1_SD_PIN_SEL			0x54
#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL		0x7C
#define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)

#define SDIO_BOOT_MAIN_CTL			0x0

#define MMC_CAP_HSE_MASK	(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
/* Select all SD UHS type I SDR speed above 50MB/s */
#define MMC_CAP_UHS_I_SDR_MASK	(MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)

enum cfg_core_ver {
	SDIO_CFG_CORE_V1 = 1,
	SDIO_CFG_CORE_V2,
};

struct sdhci_brcmstb_saved_regs {
	u32 sd_pin_sel;
	u32 phy_sw_mode0_rxctrl;
	u32 max_50mhz_mode;
	u32 boot_main_ctl;
};

struct brcmstb_match_priv {
	void (*cfginit)(struct sdhci_host *host);
	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
	void (*save_restore_regs)(struct mmc_host *mmc, int save);
	struct sdhci_ops *ops;
	const unsigned int flags;
};

struct sdhci_brcmstb_priv {
	void __iomem *cfg_regs;
	void __iomem *boot_regs;
	struct sdhci_brcmstb_saved_regs saved_regs;
	unsigned int flags;
	struct clk *base_clk;
	u32 base_freq_hz;
	const struct brcmstb_match_priv *match_priv;
};

static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
	void __iomem *cr = priv->cfg_regs;
	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;

	if (is_emmc && priv->boot_regs)
		sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);

	if (ver == SDIO_CFG_CORE_V1) {
		sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
		return;
	}

	sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
	sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
	sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
}

static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
{
	struct sdhci_host *host = mmc_priv(mmc);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
	struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
	void __iomem *cr = priv->cfg_regs;
	bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;

	if (is_emmc && priv->boot_regs)
		writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);

	if (ver == SDIO_CFG_CORE_V1) {
		writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
		return;
	}

	writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
	writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
	writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
}

static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
{
	if (save)
		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
	else
		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
}

static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
{
	if (save)
		sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
	else
		sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
}

static inline void enable_clock_gating(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
	u32 reg;

	if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK))
		return;

	reg = sdhci_readl(host, SDHCI_VENDOR);
	reg |= SDHCI_VENDOR_GATE_SDCLK_EN;
	sdhci_writel(host, reg, SDHCI_VENDOR);
}

static void brcmstb_reset(struct sdhci_host *host, u8 mask)
{
	sdhci_and_cqhci_reset(host, mask);

	/* Reset will clear this, so re-enable it */
	enable_clock_gating(host);
}

static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)
{
	u32 new_mask = (mask &  (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24;
	int ret;
	u32 reg;

	/*
	 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall
	 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA
	 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register
	 */
	new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;
	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
	sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);

	reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);

	ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask),
				       10, 10000, false,
				       host, SDHCI_SOFTWARE_RESET);

	if (ret) {
		pr_err("%s: Reset 0x%x never completed.\n",
		       mmc_hostname(host->mmc), (int)mask);
		sdhci_err_stats_inc(host, CTRL_TIMEOUT);
		sdhci_dumpregs(host);
	}
}

static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)
{
	/* take care of RESET_ALL as usual */
	if (mask & SDHCI_RESET_ALL)
		sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);

	/* cmd and/or data treated differently on this core */
	if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA))
		brcmstb_sdhci_reset_cmd_data(host, mask);