path: root/drivers/mmc/host/loongson2-mmc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Loongson-2K MMC/SDIO controller driver
 *
 * Copyright (C) 2018-2025 Loongson Technology Corporation Limited.
 *
 */

#include <linux/bitfield.h>
#include <linux/bitrev.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mmc/core.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/sd.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define LOONGSON2_MMC_REG_CTL		0x00 /* Control Register */
#define LOONGSON2_MMC_REG_PRE		0x04 /* Prescaler Register */
#define LOONGSON2_MMC_REG_CARG		0x08 /* Command Register */
#define LOONGSON2_MMC_REG_CCTL		0x0c /* Command Control Register */
#define LOONGSON2_MMC_REG_CSTS		0x10 /* Command Status Register */
#define LOONGSON2_MMC_REG_RSP0		0x14 /* Command Response Register 0 */
#define LOONGSON2_MMC_REG_RSP1		0x18 /* Command Response Register 1 */
#define LOONGSON2_MMC_REG_RSP2		0x1c /* Command Response Register 2 */
#define LOONGSON2_MMC_REG_RSP3		0x20 /* Command Response Register 3 */
#define LOONGSON2_MMC_REG_TIMER		0x24 /* Data Timeout Register */
#define LOONGSON2_MMC_REG_BSIZE		0x28 /* Block Size Register */
#define LOONGSON2_MMC_REG_DCTL		0x2c /* Data Control Register */
#define LOONGSON2_MMC_REG_DCNT		0x30 /* Data Counter Register */
#define LOONGSON2_MMC_REG_DSTS		0x34 /* Data Status Register */
#define LOONGSON2_MMC_REG_FSTS		0x38 /* FIFO Status Register */
#define LOONGSON2_MMC_REG_INT		0x3c /* Interrupt Register */
#define LOONGSON2_MMC_REG_DATA		0x40 /* Data Register */
#define LOONGSON2_MMC_REG_IEN		0x64 /* Interrupt Enable Register */

/* EMMC DLL Mode Registers */
#define LOONGSON2_MMC_REG_DLLVAL	0xf0 /* DLL Master Lock-value Register */
#define LOONGSON2_MMC_REG_DLLCTL	0xf4 /* DLL Control Register */
#define LOONGSON2_MMC_REG_DELAY		0xf8 /* DLL Delayed Parameter Register */
#define LOONGSON2_MMC_REG_SEL		0xfc /* Bus Mode Selection Register */

/* Exclusive DMA R/W Registers */
#define LOONGSON2_MMC_REG_WDMA_LO	0x400
#define LOONGSON2_MMC_REG_WDMA_HI	0x404
#define LOONGSON2_MMC_REG_RDMA_LO	0x800
#define LOONGSON2_MMC_REG_RDMA_HI	0x804

/* Bitfields of control register */
#define LOONGSON2_MMC_CTL_ENCLK		BIT(0)
#define LOONGSON2_MMC_CTL_EXTCLK	BIT(1)
#define LOONGSON2_MMC_CTL_RESET		BIT(8)

/* Bitfields of prescaler register */
#define LOONGSON2_MMC_PRE		GENMASK(9, 0)
#define LOONGSON2_MMC_PRE_EN		BIT(31)

/* Bitfields of command control register */
#define LOONGSON2_MMC_CCTL_INDEX	GENMASK(5, 0)
#define LOONGSON2_MMC_CCTL_HOST		BIT(6)
#define LOONGSON2_MMC_CCTL_START	BIT(8)
#define LOONGSON2_MMC_CCTL_WAIT_RSP	BIT(9)
#define LOONGSON2_MMC_CCTL_LONG_RSP	BIT(10)
#define LOONGSON2_MMC_CCTL_ABORT	BIT(12)
#define LOONGSON2_MMC_CCTL_CHECK	BIT(13)
#define LOONGSON2_MMC_CCTL_SDIO		BIT(14)
#define LOONGSON2_MMC_CCTL_CMD6		BIT(18)

/* Bitfields of command status register */
#define LOONGSON2_MMC_CSTS_INDEX	GENMASK(7, 0)
#define LOONGSON2_MMC_CSTS_ON		BIT(8)
#define LOONGSON2_MMC_CSTS_RSP		BIT(9)
#define LOONGSON2_MMC_CSTS_TIMEOUT	BIT(10)
#define LOONGSON2_MMC_CSTS_END		BIT(11)
#define LOONGSON2_MMC_CSTS_CRC_ERR	BIT(12)
#define LOONGSON2_MMC_CSTS_AUTO_STOP	BIT(13)
#define LOONGSON2_MMC_CSTS_FIN		BIT(14)

/* Bitfields of data timeout register */
#define LOONGSON2_MMC_DTIMR		GENMASK(23, 0)

/* Bitfields of block size register */
#define LOONGSON2_MMC_BSIZE		GENMASK(11, 0)

/* Bitfields of data control register */
#define LOONGSON2_MMC_DCTL_BNUM		GENMASK(11, 0)
#define LOONGSON2_MMC_DCTL_START	BIT(14)
#define LOONGSON2_MMC_DCTL_ENDMA	BIT(15)
#define LOONGSON2_MMC_DCTL_WIDE		BIT(16)
#define LOONGSON2_MMC_DCTL_RWAIT	BIT(17)
#define LOONGSON2_MMC_DCTL_IO_SUSPEND	BIT(18)
#define LOONGSON2_MMC_DCTL_IO_RESUME	BIT(19)
#define LOONGSON2_MMC_DCTL_RW_RESUME	BIT(20)
#define LOONGSON2_MMC_DCTL_8BIT_BUS	BIT(26)

/* Bitfields of sata counter register */
#define LOONGSON2_MMC_DCNT_BNUM		GENMASK(11, 0)
#define LOONGSON2_MMC_DCNT_BYTE		GENMASK(23, 12)

/* Bitfields of command status register */
#define LOONGSON2_MMC_DSTS_RXON		BIT(0)
#define LOONGSON2_MMC_DSTS_TXON		BIT(1)
#define LOONGSON2_MMC_DSTS_SBITERR	BIT(2)
#define LOONGSON2_MMC_DSTS_BUSYFIN	BIT(3)
#define LOONGSON2_MMC_DSTS_XFERFIN	BIT(4)
#define LOONGSON2_MMC_DSTS_DTIMEOUT	BIT(5)
#define LOONGSON2_MMC_DSTS_RXCRC	BIT(6)
#define LOONGSON2_MMC_DSTS_TXCRC	BIT(7)
#define LOONGSON2_MMC_DSTS_IRQ		BIT(8)
#define LOONGSON2_MMC_DSTS_START	BIT(13)
#define LOONGSON2_MMC_DSTS_RESUME	BIT(15)
#define LOONGSON2_MMC_DSTS_SUSPEND	BIT(16)

/* Bitfields of FIFO Status Register */
#define LOONGSON2_MMC_FSTS_TXFULL	BIT(11)

/* Bitfields of interrupt register */
#define LOONGSON2_MMC_INT_DFIN		BIT(0)
#define LOONGSON2_MMC_INT_DTIMEOUT	BIT(1)
#define LOONGSON2_MMC_INT_RXCRC		BIT(2)
#define LOONGSON2_MMC_INT_TXCRC		BIT(3)
#define LOONGSON2_MMC_INT_PROGERR	BIT(4)
#define LOONGSON2_MMC_INT_SDIOIRQ	BIT(5)
#define LOONGSON2_MMC_INT_CSENT		BIT(6)
#define LOONGSON2_MMC_INT_CTIMEOUT	BIT(7)
#define LOONGSON2_MMC_INT_RESPCRC	BIT(8)
#define LOONGSON2_MMC_INT_BUSYEND	BIT(9)

/* Bitfields of interrupt enable register */
#define LOONGSON2_MMC_IEN_DFIN		BIT(0)
#define LOONGSON2_MMC_IEN_DTIMEOUT	BIT(1)
#define LOONGSON2_MMC_IEN_RXCRC		BIT(2)
#define LOONGSON2_MMC_IEN_TXCRC		BIT(3)
#define LOONGSON2_MMC_IEN_PROGERR	BIT(4)
#define LOONGSON2_MMC_IEN_SDIOIRQ	BIT(5)
#define LOONGSON2_MMC_IEN_CSENT		BIT(6)
#define LOONGSON2_MMC_IEN_CTIMEOUT	BIT(7)
#define LOONGSON2_MMC_IEN_RESPCRC	BIT(8)
#define LOONGSON2_MMC_IEN_BUSYEND	BIT(9)

#define LOONGSON2_MMC_IEN_ALL		GENMASK(9, 0)
#define LOONGSON2_MMC_INT_CLEAR		GENMASK(9, 0)

/* Bitfields of DLL master lock-value register */
#define LOONGSON2_MMC_DLLVAL_DONE	BIT(8)

/* Bitfields of DLL control register */
#define LOONGSON2_MMC_DLLCTL_TIME	GENMASK(7, 0)
#define LOONGSON2_MMC_DLLCTL_INCRE	GENMASK(15, 8)
#define LOONGSON2_MMC_DLLCTL_START	GENMASK(23, 16)
#define LOONGSON2_MMC_DLLCTL_CLK_MODE	BIT(24)
#define LOONGSON2_MMC_DLLCTL_START_BIT	BIT(25)
#define LOONGSON2_MMC_DLLCTL_TIME_BPASS	GENMASK(29, 26)

#define LOONGSON2_MMC_DELAY_PAD		GENMASK(7, 0)
#define LOONGSON2_MMC_DELAY_RD		GENMASK(15, 8)

#define LOONGSON2_MMC_SEL_DATA		BIT(0)	/* 0: SDR, 1: DDR */
#define LOONGSON2_MMC_SEL_BUS		BIT(0)	/* 0: EMMC, 1: SDIO */

/* Internal dma controller registers */

/* Bitfields of Global Configuration Register */
#define LOONGSON2_MMC_DMA_64BIT_EN	BIT(0) /* 1: 64 bit support */
#define LOONGSON2_MMC_DMA_UNCOHERENT_EN	BIT(1) /* 0: cache, 1: uncache */
#define LOONGSON2_MMC_DMA_ASK_VALID	BIT(2)
#define LOONGSON2_MMC_DMA_START		BIT(3) /* DMA start operation */
#define LOONGSON2_MMC_DMA_STOP		BIT(4) /* DMA stop operation */
#define LOONGSON2_MMC_DMA_CONFIG_MASK	GENMASK_ULL(4, 0) /* DMA controller config bits mask */

/* Bitfields of ndesc_addr field of HW descriptor */
#define LOONGSON2_MMC_DMA_DESC_EN	BIT(0) /*1: The next descriptor is valid */
#define LOONGSON2_MMC_DMA_DESC_ADDR_LOW	GENMASK(31, 1)

/* Bitfields of cmd field of HW descriptor */
#define LOONGSON2_MMC_DMA_INT		BIT(1)	/* Enable DMA interrupts */
#define LOONGSON2_MMC_DMA_DATA_DIR	BIT(12) /* 1: write to device, 0: read from device */

#define LOONGSON2_MMC_DLLVAL_TIMEOUT_US		4000
#define LOONGSON2_MMC_TXFULL_TIMEOUT_US		500

/*
 * Due to a hardware design flaw, the Loongson-2K0300 may fail to recognize the
 * CMD48 (SD_READ_EXTR_SINGLE) interrupt.
 */
#define LOONGSON2_MMC_CMD48_QUIRK	BIT(0)

/* Loongson-2K1000 SDIO2 DMA routing register */
#define LS2K1000_SDIO_DMA_MASK		GENMASK(17, 15)
#define LS2K1000_DMA0_CONF		0x0
#define LS2K1000_DMA1_CONF		0x1
#define LS2K1000_DMA2_CONF		0x2
#define LS2K1000_DMA3_CONF		0x3
#define LS2K1000_DMA4_CONF		0x4

/* Loongson-2K0500 SDIO2 DMA routing register */
#define LS2K0500_SDIO_DMA_MASK		GENMASK(15, 14)
#define LS2K0500_DMA0_CONF		0x1
#define LS2K0500_DMA1_CONF		0x2
#define LS2K0500_DMA2_CONF		0x3

enum loongson2_mmc_state {
	STATE_NONE,
	STATE_FINALIZE,
	STATE_CMDSENT,
	STATE_RSPFIN,
	STATE_XFERFINISH,
	STATE_XFERFINISH_RSPFIN,
};

struct loongson2_dma_desc {
	u32 ndesc_addr;
	u32 mem_addr;
	u32 apb_addr;
	u32 len;
	u32 step_len;
	u32 step_times;
	u32 cmd;
	u32 stats;
	u32 high_ndesc_addr;
	u32 high_mem_addr;
	u32 reserved[2];
} __packed;

struct loongson2_mmc_host {
	struct device *dev;
	struct mmc_request *mrq;
	struct regmap *regmap;
	struct resource *res;
	struct clk *clk;
	u32 current_clk;
	void *sg_cpu;
	dma_addr_t sg_dma;
	int dma_complete;
	struct dma_chan *chan;
	int cmd_is_stop;
	int bus_width;
	spinlock_t lock; /* Prevent races with irq handler */
	enum loongson2_mmc_state state;
	const struct loongson2_mmc_pdata *pdata;
};

struct loongson2_mmc_pdata {
	u32 flags;
	const struct regmap_config *regmap_config;
	void (*reorder_cmd_data