// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved.
*/
#include <dt-bindings/memory/nvidia,tegra264.h>
#include <linux/interconnect.h>
#include <linux/of_device.h>
#include <linux/tegra-icc.h>
#include <soc/tegra/bpmp.h>
#include <soc/tegra/mc.h>
#include "mc.h"
#include "tegra264-bwmgr.h"
/*
* MC Client entries are sorted in the increasing order of the
* override and security register offsets.
*/
static const struct tegra_mc_client tegra264_mc_clients[] = {
{
.id = TEGRA264_MEMORY_CLIENT_PTCR,
.name = "ptcr",
}, {
.id = TEGRA264_MEMORY_CLIENT_HOST1XR,
.name = "host1xr",
}, {
.id = TEGRA264_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
}, {
.id = TEGRA264_MEMORY_CLIENT_PSCR,
.name = "pscr",
}, {
.id = TEGRA264_MEMORY_CLIENT_PSCW,
.name = "pscw",
}, {
.id = TEGRA264_MEMORY_CLIENT_ISP0R,
.name = "isp0r",
}, {
.id = TEGRA264_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
}, {
.id = TEGRA264_MEMORY_CLIENT_ISP0W,
.name = "isp0w",
}, {
.id = TEGRA264_MEMORY_CLIENT_ISP1W,
.name = "isp1w",
}, {
.id = TEGRA264_MEMORY_CLIENT_ISPFALCONR,
.name = "ispfalconr",
}, {
.id = TEGRA264_MEMORY_CLIENT_ISPFALCONW,
.name = "ispfalconw",
}, {
.id = TEGRA264_MEMORY_CLIENT_MGBE2R,
.name = "mgbe2r",
}, {
.id = TEGRA264_MEMORY_CLIENT_OFAR2MC,
.name = "ofar2mc",
}, {
.id = TEGRA264_MEMORY_CLIENT_OFAW2MC,
.name = "ofaw2mc",
}, {
.id = TEGRA264_MEMORY_CLIENT_MGBE2W,
.name = "mgbe2w",
}, {
.id = TEGRA264_MEMORY_CLIENT_MGBE3R,
.name = "mgbe3r",
}, {
.id = TEGRA264_MEMORY_CLIENT_MGBE3W,
.name = "mgbe3w",
}, {
.id = TEGRA264_MEMORY_CLIENT_SEU1RD,
.name = "seu1rd",
}, {
.id = TEGRA264_MEMORY_CLIENT_SEU1WR,
.name = "seu1wr",
}, {
.id = TEGRA264_MEMORY_CLIENT_VICR,
.name = "vicr",
.bpmp_id = TEGRA264_BWMGR_VIC,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA264_MEMORY_CLIENT_VICW,
.name = "vicw",
.bpmp_id = TEGRA264_BWMGR_VIC,
.type = TEGRA_ICC_NISO,
}, {
.id = TEGRA264_MEMORY_CLIENT_VIW,
.name = "viw",
}, {
.id =