path: root/drivers/media/platform/qcom/venus/core.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
 * Copyright (C) 2017 Linaro Ltd.
 */

#ifndef __VENUS_CORE_H_
#define __VENUS_CORE_H_

#include <linux/bitops.h>
#include <linux/list.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>

#include "dbgfs.h"
#include "hfi.h"
#include "hfi_platform.h"
#include "hfi_helper.h"

#define VDBGL	"VenusLow : "
#define VDBGM	"VenusMed : "
#define VDBGH	"VenusHigh: "
#define VDBGFW	"VenusFW  : "

#define VIDC_CLKS_NUM_MAX		4
#define VIDC_VCODEC_CLKS_NUM_MAX	2
#define VIDC_RESETS_NUM_MAX		2
#define VIDC_MAX_HIER_CODING_LAYER 6

#define VENUS_MAX_FPS			240

extern int venus_fw_debug;

struct freq_tbl {
	unsigned int load;
	unsigned long freq;
};

struct reg_val {
	u32 reg;
	u32 value;
};

struct bw_tbl {
	u32 mbs_per_sec;
	u32 avg;
	u32 peak;
	u32 avg_10bit;
	u32 peak_10bit;
};

enum vpu_version {
	VPU_VERSION_AR50,
	VPU_VERSION_AR50_LITE,
	VPU_VERSION_IRIS1,
	VPU_VERSION_IRIS2,
	VPU_VERSION_IRIS2_1,
};

struct firmware_version {
	u32 major;
	u32 minor;
	u32 rev;
};

struct venus_resources {
	u64 dma_mask;
	const struct freq_tbl *freq_tbl;
	unsigned int freq_tbl_size;
	const struct bw_tbl *bw_tbl_enc;
	unsigned int bw_tbl_enc_size;
	const struct bw_tbl *bw_tbl_dec;
	unsigned int bw_tbl_dec_size;
	const struct reg_val *reg_tbl;
	unsigned int reg_tbl_size;
	const struct hfi_ubwc_config *ubwc_conf;
	const char * const clks[VIDC_CLKS_NUM_MAX];
	unsigned int clks_num;
	const char * const vcodec0_clks[VIDC_VCODEC_CLKS_NUM_MAX];
	const char * const vcodec1_clks[VIDC_VCODEC_CLKS_NUM_MAX];
	unsigned int vcodec_clks_num;
	const char **vcodec_pmdomains;
	unsigned int vcodec_pmdomains_num;
	const char **opp_pmdomain;
	unsigned int vcodec_num;
	const char * const resets[VIDC_RESETS_NUM_MAX];
	unsigned int resets_num;
	enum hfi_version hfi_version;
	enum vpu_version vpu_version;
	u8 num_vpp_pipes;
	u32 max_load;
	unsigned int vmem_id;
	u32 vmem_size;
	u32 vmem_addr;
	u32 cp_start;
	u32 cp_size;
	u32 cp_nonpixel_start;
	u32 cp_nonpixel_size;
	const char *fwname;
	const char *enc_nodename;
	const char *dec_nodename;
	const struct firmware_version *min_fw;
};

enum venus_fmt {
	VENUS_FMT_NV12			= 0,
	VENUS_FMT_QC08C			= 1,
	VENUS_FMT_QC10C			= 2,
	VENUS_FMT_P010			= 3,
	VENUS_FMT_H264			= 4,
	VENUS_FMT_VP8			= 5,
	VENUS_FMT_VP9			= 6,
	VENUS_FMT_HEVC			= 7,
	VENUS_FMT_VC1_ANNEX_G		= 8,
	VENUS_FMT_VC1_ANNEX_L		= 9,
	VENUS_FMT_MPEG4			= 10,
	VENUS_FMT_MPEG2			= 11,
	VENUS_FMT_H263			= 12,
	VENUS_FMT_XVID			= 13,
};

struct venus_format {
	u32 pixfmt;
	unsigned int num_planes;
	u32 type;
	u32 flags;
};

/**
 * struct venus_core - holds core parameters valid for all instances
 *
 * @base:	IO memory base address
 * @vbif_base:	IO memory vbif base address
 * @cpu_base:	IO memory cpu base address
 * @cpu_cs_base:	IO memory cpu_cs base address
 * @cpu_ic_base:	IO memory cpu_ic base address
 * @wrapper_base:	IO memory wrapper base address
 * @wrapper_tz_base:	IO memory wrapper TZ base address
 * @aon_base:	AON base address
 * @irq:		Venus irq
 * @clks:	an array of struct clk pointers
 * @vcodec0_clks: an array of vcodec0 struct clk pointers
 * @vcodec1_clks: an array of vcodec1 struct clk pointers
 * @video_path: an interconnect handle to video to/from memory path
 * @cpucfg_path: an interconnect handle to cpu configuration path
 * @pmdomains:	a pointer to a list of pmdomains
 * @opp_pmdomain: an OPP power-domain
 * @resets: an array of reset signals
 * @vdev_dec:	a reference to video device structure for decoder instances
 * @vdev_enc:	a reference to video device structure for encoder instances
 * @v4l2_dev:	a holder for v4l2 device structure
 * @res:		a reference to venus resources structure
 * @dev:		convenience struct device pointer
 * @dev_dec:	convenience struct device pointer for decoder device
 * @dev_enc:	convenience struct device pointer for encoder device
 * @use_tz:	a flag that suggests presence of trustzone
 * @fw:		structure of firmware parameters
 * @lock:	a lock for this strucure
 * @instances:	a list_head of all instances
 * @insts_count:	num of instances
 * @state:	the state of the venus core
 * @done:	a completion for sync HFI operations
 * @error:	an error returned during last HFI sync operations
 * @sys_error:	an error flag that signal system error event
 * @sys_err_done: a waitqueue to wait for system error recovery end
 * @core_ops:	the core operations
 * @pm_ops:	a pointer to pm operations
 * @pm_lock:	a lock for PM operations
 * @enc_codecs:	encoders supported by this core
 * @dec_codecs:	decoders supported by this core
 * @max_sessions_supported:	holds the maximum number of sessions
 * @priv:	a private filed for HFI operations
 * @ops:		the core HFI operations
 * @work:	a delayed work for handling system fatal error
 * @caps:	an array of supported HFI capabilities
 * @codecs_count: platform codecs count
 * @core0_usage_count: usage counter for core0
 * @core1_usage_count: usage counter for core1
 * @root:	debugfs root directory
 * @venus_ver:	the venus firmware version
 * @dump_core:	a flag indicating that a core dump is required
 * @ocs:	OF changeset pointer
 * @hwmode_dev:	a flag indicating that HW_CTRL_TRIGGER is used in clock driver
 */
struct venus_core {
	void __iomem *base;
	void __iomem *vbif_base;
	void __iomem *cpu_base;
	void __iomem *cpu_cs_base;
	void __iomem *cpu_ic_base;
	void __iomem *wrapper_base;
	void __iomem *wrapper_tz_base;
	void __iomem *aon_base;
	int irq;
	struct clk *clks[VIDC_CLKS_NUM_MAX];
	struct clk *vcodec0_clks[VIDC_VCODEC_CLKS_NUM_MAX];
	struct clk *vcodec1_clks[VIDC_VCODEC_CLKS_NUM_MAX];
	struct icc_path *video_path;
	struct icc_path *cpucfg_path;
	struct dev_pm_domain_list *pmdomains;
	struct dev_pm_domain_list *opp_pmdomain;
	struct reset_control *resets[VIDC_RESETS_NUM_MAX];
	struct video_device *vdev_dec;
	struct video_device *vdev_enc;
	struct v4l2_device v4l2_dev;
	const struct venus_resources *res;
	struct device *dev;
	struct device *dev_dec;
	struct device *dev_enc;
	unsigned int use_tz;
	struct video_firmware {
		struct device *dev;
		struct iommu_domain *iommu_domain;
		size_t mapped_mem_size;
		phys_addr_t mem_phys;
		size_t mem_size;
	} fw;
	struct mutex lock;
	struct list_head instances;
	atomic_t insts_count;
	unsigned int state;
	struct completion done;
	unsigned int error;
	unsigned long sys_error;
	wait_queue_head_t sys_err_done;
	const struct hfi_core_ops *core_ops;
	const struct venus_pm_ops *pm_ops;
	struct mutex pm_lock;
	unsigned long enc_codecs;
	unsigned long dec_codecs;
	unsigned int max_sessions_supported;
	void *priv;
	const struct hfi_ops *ops;
	struct delayed_work work;
	struct hfi_plat_caps caps[MAX_CODEC_NUM];
	unsigned int codecs_count;
	unsigned int core0_usage_count;
	unsigned int core1_usage_count;
	struct dentry *root;
	struct firmware_version venus_ver;
	unsigned long dump_core;
	struct of_changeset *ocs;
	bool hwmode_dev;
};

struct vdec_controls {
	u32 post_loop_deb_mode;
	u32 profile;
	u32 level;
	u32 display_delay;
	u32 display_delay_enable;
	u64 conceal_color;
};

struct venc_controls {
	u16 gop_size;
	u32 num_p_frames;
	u32 num_b_frames;
	u32 bitrate_mode;
	u32 bitrate;
	u32 bitrate_peak;
	u32 rc_enable;
	u32 const_quality;
	u32 frame_skip_mode;
	u32 layer_bitrate;

	u32 h264_i_period;
	u32 h264_entropy_mode;
	u32 h264_i_qp;
	u32 h264_p_qp;
	u32 h264_b_qp;
	u32 h264_min_qp;
	u32 h264_max_qp;
	u32 h264_i_min_qp;
	u32 h264_i_max_qp;
	u32 h264_p_min_qp;
	u32 h264_p_max_qp;
	u32 h264_b_min_qp;
	u32