path: root/drivers/media/platform/chips-media/wave5/wave5-vpu.c

// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
 * Wave5 series multi-standard codec IP - platform driver
 *
 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include "wave5-vpu.h"
#include "wave5-regdefine.h"
#include "wave5-vpuconfig.h"
#include "wave5.h"

#define VPU_PLATFORM_DEVICE_NAME "vdec"
#define VPU_CLK_NAME "vcodec"

#define WAVE5_IS_ENC BIT(0)
#define WAVE5_IS_DEC BIT(1)

struct wave5_match_data {
	int flags;
	const char *fw_name;
	u32 sram_size;
};

static int vpu_poll_interval = 5;
module_param(vpu_poll_interval, int, 0644);

int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)
{
	int ret;

	ret = wait_for_completion_timeout(&inst->irq_done,
					  msecs_to_jiffies(timeout));
	if (!ret)
		return -ETIMEDOUT;

	reinit_completion(&inst->irq_done);

	return 0;
}

static void wave5_vpu_handle_irq(void *dev_id)
{
	u32 seq_done;
	u32 cmd_done;
	u32 irq_reason;
	u32 irq_subreason;
	struct vpu_instance *inst, *tmp;
	struct vpu_device *dev = dev_id;
	int val;
	unsigned long flags;

	irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
	seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);
	cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);
	wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason);
	wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);

	spin_lock_irqsave(&dev->irq_spinlock, flags);
	list_for_each_entry_safe(inst, tmp, &dev->instances, list) {

		if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) ||
		    irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) {
			if (dev->product_code == WAVE515_CODE &&
			    (cmd_done & BIT(inst->id))) {
				cmd_done &= ~BIT(inst->id);
				wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,
							 cmd_done);
				complete(&inst->irq_done);
			} else if (seq_done & BIT(inst->id)) {
				seq_done &= ~BIT(inst->id);
				wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO,
							 seq_done);
				complete(&inst->irq_done);
			}
		}

		if (irq_reason & BIT(INT_WAVE5_DEC_PIC) ||
		    irq_reason & BIT(INT_WAVE5_ENC_PIC)) {
			if (cmd_done & BIT(inst->id)) {
				cmd_done &= ~BIT(inst->id);
				if (dev->irq >= 0) {
					irq_subreason =
						wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
					if (!(irq_subreason & BIT(INT_WAVE5_DEC_PIC)))
						wave5_vdi_write_register(dev,
									 W5_RET_QUEUE_CMD_DONE_INST,
									 cmd_done);
				}
				val = BIT(INT_WAVE5_DEC_PIC);
				kfifo_in(&inst->irq_status, &val, sizeof(int));
			}
		}
	}
	spin_unlock_irqrestore(&dev->irq_spinlock, flags);

	if (dev->irq < 0)
		up(&dev->irq_sem);
}

static irqreturn_t wave5_vpu_irq(int irq, void *dev_id)
{
	struct vpu_device *dev = dev_id;

	if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) {
		wave5_vpu_handle_irq(dev);
		return IRQ_WAKE_THREAD;
	}

	return IRQ_HANDLED;
}

static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)
{
	struct vpu_device *dev = dev_id;
	struct vpu_instance *inst, *tmp;
	int irq_status, ret;

	mutex_lock(&dev->irq_lock);
	list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
		while (kfifo_len(&inst->irq_status)) {
			ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
			if (!ret)
				break;

			inst->ops->finish_process(inst);
		}
	}
	mutex_unlock(&dev->irq_lock);

	return IRQ_HANDLED;
}

static void wave5_vpu_irq_work_fn(struct kthread_work *work)
{
	struct vpu_device *dev = container_of(work, struct vpu_device, work);

	if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS))
		wave5_vpu_handle_irq(dev);
}

static enum hrtimer_restart wave5_vpu_timer_callback(struct hrtimer *timer)
{
	struct vpu_device *dev =
			container_of(timer, struct vpu_device, hrtimer);

	kthread_queue_work(dev->worker, &dev->work);
	hrtimer_forward_now(timer, ns_to_ktime(vpu_poll_interval * NSEC_PER_MSEC));

	return HRTIMER_RESTART;
}

static int irq_thread(void *data)
{
	struct vpu_device *dev = (struct vpu_device *)data;
	struct vpu_instance *inst, *tmp;
	int irq_status, ret;

	while (!kthread_should_stop()) {
		if (down_interruptible(&dev->irq_sem))
			continue;

		if (kthread_should_stop())
			break;

		mutex_lock(&dev->irq_lock);
		list_for_each_entry_safe(inst, tmp, &dev->instances, list) {
			while (kfifo_len(&inst->irq_status)) {
				ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int));
				if (!ret)
					break;

				inst->ops->finish_process(inst);
			}
		}
		mutex_unlock(&dev->irq_lock);
	}

	return 0;
}

static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name,
				   u32 *revision)
{
	const struct firmware *fw;
	int ret;
	unsigned int product_id;

	ret = request_firmware(&fw, fw_name, dev);
	if (ret) {
		dev_err(dev, "request_firmware, fail: %d\n", ret);
		return ret;
	}

	ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size);
	if (ret) {
		dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);
		release_firmware(fw);
		return ret;
	}
	release_firmware(fw);

	ret = wave5_vpu_get_version_info(dev, revision, &product_id);
	if (ret) {
		dev_err(dev, "vpu_get_version_info fail: %d\n", ret);
		return ret;
	}

	dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",
		__func__, product_id, *revision);

	return 0;
}

static __maybe_unused int wave5_pm_suspend(struct device *dev)
{
	struct vpu_device *vpu = dev_get_drvdata(dev);

	if (pm_runtime_suspended(dev))
		return 0;

	if (vpu->irq < 0)
		hrtimer_cancel(&vpu->hrtimer);

	wave5_vpu_sleep_wake(dev, true, NULL, 0);
	clk_bulk_disable_unprepare(vpu->num_clks, vpu-><