// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/interconnect/qcom,sdx65.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sdx65.h"
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SDX65_MASTER_LLCC,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_EBI1 },
};
static struct qcom_icc_node acm_tcu = {
.name = "acm_tcu",
.id = SDX65_MASTER_TCU_0,
.channels = 1,
.buswidth = 8,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SDX65_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SDX65_SLAVE_LLCC },
};
static struct qcom_icc_node xm_apps_rdwr = {
.name = "xm_apps_rdwr",
.id = SDX65_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SDX65_SLAVE_LLCC,
SDX65_SLAVE_MEM_NOC_SNOC,
SDX65_SLAVE_MEM_NOC_PCIE_SNOC
},
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.id = SDX65_MASTER_AUDIO,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_blsp1 = {
.name = "qhm_blsp1",
.id = SDX65_MASTER_BLSP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_ANOC_SNOC },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SDX65_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 26,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_TCU
},
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.id = SDX65_MASTER_QPIC,
.channels = 1,
.buswidth = 4,
.num_links = 4,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
.id = SDX65_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX65_SLAVE_SERVICE_SNOC },
};
static struct qcom_icc_node qhm_spmi_fetcher1 = {
.name = "qhm_spmi_fetcher1",
.id = SDX65_MASTER_SPMI_FETCHER,
.channels = 1,
.buswidth = 4,
.num_links = 2,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_ANOC_SNOC
},
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.id = SDX65_MASTER_ANOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 29,
.links = { SDX65_SLAVE_AOSS,
SDX65_SLAVE_APPSS,
SDX65_SLAVE_AUDIO,
SDX65_SLAVE_BLSP_1,
SDX65_SLAVE_CLK_CTL,
SDX65_SLAVE_CRYPTO_0_CFG,
SDX65_SLAVE_CNOC_DDRSS,
SDX65_SLAVE_ECC_CFG,
SDX65_SLAVE_IMEM_CFG,
SDX65_SLAVE_IPA_CFG,
SDX65_SLAVE_CNOC_MSS,
SDX65_SLAVE_PCIE_PARF,
SDX65_SLAVE_PDM,
SDX65_SLAVE_PRNG,
SDX65_SLAVE_QDSS_CFG,
SDX65_SLAVE_QPIC,
SDX65_SLAVE_SDCC_1,
SDX65_SLAVE_SNOC_CFG,
SDX65_SLAVE_SPMI_FETCHER,
SDX65_SLAVE_SPMI_VGI_COEX,
SDX65_SLAVE_TCSR,
SDX65_SLAVE_TLMM,
SDX65_SLAVE_USB3,
SDX65_SLAVE_USB3_PHY_CFG,
SDX65_SLAVE_SNOC_MEM_NOC_GC,
SDX65_SLAVE_IMEM,
SDX65_SLAVE_PCIE_0,
SDX65_SLAVE_QDSS_STM