path: root/drivers/clk/samsung/clk-artpec9.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
 *             https://www.samsung.com
 * Copyright (c) 2025  Axis Communications AB.
 *             https://www.axis.com
 *
 * Common Clock Framework support for ARTPEC-9 SoC.
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/axis,artpec9-clk.h>

#include "clk.h"
#include "clk-exynos-arm64.h"

/* NOTE: Must be equal to the last clock ID increased by one */
#define CMU_CMU_NR_CLK				(CLK_DOUT_CMU_VIO_AUDIO + 1)
#define CMU_BUS_NR_CLK				(CLK_MOUT_BUS_ACLK_USER + 1)
#define CMU_CORE_NR_CLK				(CLK_MOUT_CORE_ACLK_USER + 1)
#define CMU_CPUCL_NR_CLK			(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG + 1)
#define CMU_FSYS0_NR_CLK			(CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 + 1)
#define CMU_FSYS1_NR_CLK			(CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK + 1)
#define CMU_IMEM_NR_CLK				(CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
#define CMU_PERI_NR_CLK				(CLK_GOUT_PERI_UART2_SCLK_UART + 1)

/* Register Offset definitions for CMU_CMU (0x12c00000) */
#define PLL_LOCKTIME_PLL_AUDIO					0x0000
#define PLL_LOCKTIME_PLL_SHARED0				0x0004
#define PLL_LOCKTIME_PLL_SHARED1				0x0008
#define PLL_CON0_PLL_AUDIO					0x0100
#define PLL_CON0_PLL_SHARED0					0x0120
#define PLL_CON0_PLL_SHARED1					0x0140
#define CLK_CON_MUX_CLKCMU_BUS					0x1000
#define CLK_CON_MUX_CLKCMU_CDC_CORE				0x1004
#define CLK_CON_MUX_CLKCMU_CORE_MAIN				0x1008
#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH				0x100c
#define CLK_CON_MUX_CLKCMU_VIO_AUDIO				0x1010
#define CLK_CON_MUX_CLKCMU_DLP_CORE				0x1014
#define CLK_CON_MUX_CLKCMU_FSYS0_BUS				0x1018
#define CLK_CON_MUX_CLKCMU_FSYS0_IP				0x101c
#define CLK_CON_MUX_CLKCMU_FSYS1_BUS				0x1020
#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN0				0x1024
#define CLK_CON_MUX_CLKCMU_FSYS1_SCAN1				0x1028
#define CLK_CON_MUX_CLKCMU_GPU_2D				0x102c
#define CLK_CON_MUX_CLKCMU_GPU_3D				0x1030
#define CLK_CON_MUX_CLKCMU_IMEM_ACLK				0x1034
#define CLK_CON_MUX_CLKCMU_IMEM_CA5				0x1038
#define CLK_CON_MUX_CLKCMU_IMEM_JPEG				0x103c
#define CLK_CON_MUX_CLKCMU_IMEM_SSS				0x1040
#define CLK_CON_MUX_CLKCMU_IPA_CORE				0x1044
#define CLK_CON_MUX_CLKCMU_MIF_BUSP				0x1048
#define CLK_CON_MUX_CLKCMU_MIF_SWITCH				0x104c
#define CLK_CON_MUX_CLKCMU_PERI_DISP				0x1050
#define CLK_CON_MUX_CLKCMU_PERI_IP				0x1054
#define CLK_CON_MUX_CLKCMU_RSP_CORE				0x1058
#define CLK_CON_MUX_CLKCMU_TRFM					0x105c
#define CLK_CON_MUX_CLKCMU_VIO_CORE				0x1060
#define CLK_CON_MUX_CLKCMU_VIO_CORE_L				0x1064
#define CLK_CON_MUX_CLKCMU_VIP0					0x1068
#define CLK_CON_MUX_CLKCMU_VIP1					0x106c
#define CLK_CON_MUX_CLKCMU_VPP_CORE				0x1070
#define CLK_CON_DIV_CLKCMU_ADD					0x1800
#define CLK_CON_DIV_CLKCMU_BUS					0x1804
#define CLK_CON_DIV_CLKCMU_CDC_CORE				0x1808
#define CLK_CON_DIV_CLKCMU_CORE_MAIN				0x180c
#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH				0x1810
#define CLK_CON_DIV_CLKCMU_DLP_CORE				0x1814
#define CLK_CON_DIV_CLKCMU_FSYS0_BUS				0x1818
#define CLK_CON_DIV_CLKCMU_FSYS0_IP				0x181c
#define CLK_CON_DIV_CLKCMU_FSYS1_BUS				0x1820
#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN0				0x1824
#define CLK_CON_DIV_CLKCMU_FSYS1_SCAN1				0x1828
#define CLK_CON_DIV_CLKCMU_GPU_2D				0x182c
#define CLK_CON_DIV_CLKCMU_GPU_3D				0x1830
#define CLK_CON_DIV_CLKCMU_IMEM_ACLK				0x1834
#define CLK_CON_DIV_CLKCMU_IMEM_CA5				0x1838
#define CLK_CON_DIV_CLKCMU_IMEM_JPEG				0x183c
#define CLK_CON_DIV_CLKCMU_IMEM_SSS				0x1840
#define CLK_CON_DIV_CLKCMU_IPA_CORE				0x1844
#define CLK_CON_DIV_CLKCMU_LCPU					0x1848
#define CLK_CON_DIV_CLKCMU_MIF_BUSP				0x184c
#define CLK_CON_DIV_CLKCMU_MIF_SWITCH				0x1850
#define CLK_CON_DIV_CLKCMU_PERI_DISP				0x1854
#define CLK_CON_DIV_CLKCMU_PERI_IP				0x1858
#define CLK_CON_DIV_CLKCMU_RSP_CORE				0x185c
#define CLK_CON_DIV_CLKCMU_TRFM					0x1860
#define CLK_CON_DIV_CLKCMU_VIO_AUDIO				0x1864
#define CLK_CON_DIV_CLKCMU_VIO_CORE				0x1868
#define CLK_CON_DIV_CLKCMU_VIO_CORE_L				0x186c
#define CLK_CON_DIV_CLKCMU_VIP0					0x1870
#define CLK_CON_DIV_CLKCMU_VIP1					0x1874
#define CLK_CON_DIV_CLKCMU_VPP_CORE				0x1878
#define CLK_CON_DIV_PLL_SHARED0_DIV2				0x187c
#define CLK_CON_DIV_PLL_SHARED0_DIV3				0x1880
#define CLK_CON_DIV_PLL_SHARED0_DIV4				0x1884
#define CLK_CON_DIV_PLL_SHARED1_DIV2				0x1888
#define CLK_CON_DIV_PLL_SHARED1_DIV3				0x188c
#define CLK_CON_DIV_PLL_SHARED1_DIV4				0x1890

static const unsigned long cmu_cmu_clk_regs[] __initconst = {
	PLL_LOCKTIME_PLL_AUDIO,
	PLL_LOCKTIME_PLL_SHARED0,
	PLL_LOCKTIME_PLL_SHARED1,
	PLL_CON0_PLL_AUDIO,
	PLL_CON0_PLL_SHARED0,
	PLL_CON0_PLL_SHARED1,
	CLK_CON_MUX_CLKCMU_BUS,
	CLK_CON_MUX_CLKCMU_CDC_CORE,
	CLK_CON_MUX_CLKCMU_CORE_MAIN,
	CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
	CLK_CON_MUX_CLKCMU_DLP_CORE,
	CLK_CON_MUX_CLKCMU_FSYS0_BUS,
	CLK_CON_MUX_CLKCMU_FSYS0_IP,
	CLK_CON_MUX_CLKCMU_FSYS1_BUS,
	CLK_CON_MUX_CLKCMU_FSYS1_SCAN0,
	CLK_CON_MUX_CLKCMU_FSYS1_SCAN1,
	CLK_CON_MUX_CLKCMU_GPU_2D,
	CLK_CON_MUX_CLKCMU_GPU_3D,
	CLK_CON_MUX_CLKCMU_IMEM_ACLK,
	CLK_CON_MUX_CLKCMU_IMEM_CA5,
	CLK_CON_MUX_CLKCMU_IMEM_JPEG,
	CLK_CON_MUX_CLKCMU_IMEM_SSS,
	CLK_CON_MUX_CLKCMU_IPA_CORE,
	CLK_CON_MUX_CLKCMU_MIF_BUSP,
	CLK_CON_MUX_CLKCMU_MIF_SWITCH,
	CLK_CON_MUX_CLKCMU_PERI_DISP,
	CLK_CON_MUX_CLKCMU_PERI_IP,
	CLK_CON_MUX_CLKCMU_RSP_CORE,
	CLK_CON_MUX_CLKCMU_TRFM,
	CLK_CON_MUX_CLKCMU_VIO_CORE,
	CLK_CON_MUX_CLKCMU_VIO_CORE_L,
	CLK_CON_MUX_CLKCMU_VIP0,
	CLK_CON_MUX_CLKCMU_VIP1,
	CLK_CON_MUX_CLKCMU_VPP_CORE,
	CLK_CON_DIV_CLKCMU_ADD,
	CLK_CON_DIV_CLKCMU_BUS,
	CLK_CON_DIV_CLKCMU_CDC_CORE,
	CLK_CON_DIV_CLKCMU_CORE_MAIN,
	CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
	CLK_CON_DIV_CLKCMU_VIO_AUDIO,
	CLK_CON_DIV_CLKCMU_DLP_CORE,
	CLK_CON_DIV_CLKCMU_FSYS0_BUS,
	CLK_CON_DIV_CLKCMU_FSYS0_IP,
	CLK_CON_DIV_CLKCMU_FSYS1_BUS,
	CLK_CON_DIV_CLKCMU_FSYS1_SCAN0,
	CLK_CON_DIV_CLKCMU_FSYS1_SCAN1,
	CLK_CON_DIV_CLKCMU_GPU_2D,
	CLK_CON_DIV_CLKCMU_GPU_3D,
	CLK_CON_DIV_CLKCMU_IMEM_ACLK,
	CLK_CON_DIV_CLKCMU_IMEM_CA5,
	CLK_CON_DIV_CLKCMU_IMEM_JPEG,
	CLK_CON_DIV_CLKCMU_IMEM_SSS,
	CLK_CON_DIV_CLKCMU_IPA_CORE,
	CLK_CON_DIV_CLKCMU_LCPU,
	CLK_CON_DIV_CLKCMU_MIF_BUSP,
	CLK_CON_DIV_CLKCMU_MIF_SWITCH,
	CLK_CON_DIV_CLKCMU_PERI_DISP,
	CLK_CON_DIV_CLKCMU_PERI_IP,
	CLK_CON_DIV_CLKCMU_RSP_CORE,
	CLK_CON_DIV_CLKCMU_TRFM,
	CLK_CON_DIV_CLKCMU_VIO_AUDIO,
	CLK_CON_DIV_CLKCMU_VIO_CORE,
	CLK_CON_DIV_CLKCMU_VIO_CORE_L,
	CLK_CON_DIV_CLKCMU_VIP0,
	CLK_CON_DIV_CLKCMU_VIP1,
	CLK_CON_DIV_CLKCMU_VPP_CORE,
	CLK_CON_DIV_PLL_SHARED0_DIV2