path: root/drivers/clk/meson/t7-peripherals.c

// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
 * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved.
 * Author: Jian Hu <jian.hu@amlogic.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-dualdiv.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>

#define RTC_BY_OSCIN_CTRL0	0x8
#define RTC_BY_OSCIN_CTRL1	0xc
#define RTC_CTRL		0x10
#define SYS_CLK_CTRL0		0x40
#define SYS_CLK_EN0_REG0	0x44
#define SYS_CLK_EN0_REG1	0x48
#define SYS_CLK_EN0_REG2	0x4c
#define SYS_CLK_EN0_REG3	0x50
#define CECA_CTRL0		0x88
#define CECA_CTRL1		0x8c
#define CECB_CTRL0		0x90
#define CECB_CTRL1		0x94
#define SC_CLK_CTRL		0x98
#define DSPA_CLK_CTRL0		0x9c
#define DSPB_CLK_CTRL0		0xa0
#define CLK12_24_CTRL		0xa8
#define ANAKIN_CLK_CTRL		0xac
#define MIPI_CSI_PHY_CLK_CTRL	0x10c
#define MIPI_ISP_CLK_CTRL	0x110
#define TS_CLK_CTRL		0x158
#define MALI_CLK_CTRL		0x15c
#define ETH_CLK_CTRL		0x164
#define NAND_CLK_CTRL		0x168
#define SD_EMMC_CLK_CTRL	0x16c
#define SPICC_CLK_CTRL		0x174
#define SAR_CLK_CTRL0		0x17c
#define PWM_CLK_AB_CTRL		0x180
#define PWM_CLK_CD_CTRL		0x184
#define PWM_CLK_EF_CTRL		0x188
#define PWM_CLK_AO_AB_CTRL	0x1a0
#define PWM_CLK_AO_CD_CTRL	0x1a4
#define PWM_CLK_AO_EF_CTRL	0x1a8
#define PWM_CLK_AO_GH_CTRL	0x1ac
#define SPICC_CLK_CTRL1		0x1c0
#define SPICC_CLK_CTRL2		0x1c4

#define T7_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
	MESON_COMP_SEL(t7_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

#define T7_COMP_DIV(_name, _reg, _shift, _width) \
	MESON_COMP_DIV(t7_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)

#define T7_COMP_GATE(_name, _reg, _bit, _iflags) \
	MESON_COMP_GATE(t7_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags))

static struct clk_regmap t7_rtc_dualdiv_in = {
	.data = &(struct clk_regmap_gate_data){
		.offset = RTC_BY_OSCIN_CTRL0,
		.bit_idx = 31,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_duandiv_in",
		.ops = &clk_regmap_gate_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "xtal",
		},
		.num_parents = 1,
	},
};

static const struct meson_clk_dualdiv_param t7_dualdiv_table[] = {
	{
		.n1	= 733, .m1	= 8,
		.n2	= 732, .m2	= 11,
		.dual	= 1,
	},
	{}
};

static struct clk_regmap t7_rtc_dualdiv_div = {
	.data = &(struct meson_clk_dualdiv_data){
		.n1 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 0,
			.width   = 12,
		},
		.n2 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 12,
			.width   = 12,
		},
		.m1 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 0,
			.width   = 12,
		},
		.m2 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 12,
			.width   = 12,
		},
		.dual = {
			.reg_off =