path: root/drivers/clk/meson/c3-peripherals.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Amlogic C3 Peripherals Clock Controller Driver
 *
 * Copyright (c) 2023 Amlogic, inc.
 * Author: Chuan Liu <chuan.liu@amlogic.com>
 */

#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-regmap.h"
#include "clk-dualdiv.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>

#define RTC_BY_OSCIN_CTRL0			0x8
#define RTC_BY_OSCIN_CTRL1			0xc
#define RTC_CTRL				0x10
#define SYS_CLK_EN0_REG0			0x44
#define SYS_CLK_EN0_REG1			0x48
#define SYS_CLK_EN0_REG2			0x4c
#define CLK12_24_CTRL				0xa8
#define AXI_CLK_EN0				0xac
#define VDIN_MEAS_CLK_CTRL			0xf8
#define VAPB_CLK_CTRL				0xfc
#define MIPIDSI_PHY_CLK_CTRL			0x104
#define GE2D_CLK_CTRL				0x10c
#define ISP0_CLK_CTRL				0x110
#define DEWARPA_CLK_CTRL			0x114
#define VOUTENC_CLK_CTRL			0x118
#define VDEC_CLK_CTRL				0x140
#define VDEC3_CLK_CTRL				0x148
#define TS_CLK_CTRL				0x158
#define ETH_CLK_CTRL				0x164
#define NAND_CLK_CTRL				0x168
#define SD_EMMC_CLK_CTRL			0x16c
#define SPICC_CLK_CTRL				0x174
#define GEN_CLK_CTRL				0x178
#define SAR_CLK_CTRL0				0x17c
#define PWM_CLK_AB_CTRL				0x180
#define PWM_CLK_CD_CTRL				0x184
#define PWM_CLK_EF_CTRL				0x188
#define PWM_CLK_GH_CTRL				0x18c
#define PWM_CLK_IJ_CTRL				0x190
#define PWM_CLK_KL_CTRL				0x194
#define PWM_CLK_MN_CTRL				0x198
#define VC9000E_CLK_CTRL			0x19c
#define SPIFC_CLK_CTRL				0x1a0
#define NNA_CLK_CTRL				0x220

#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
	MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)

#define C3_COMP_DIV(_name, _reg, _shift, _width) \
	MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)

#define C3_COMP_GATE(_name, _reg, _bit) \
	MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT)

static struct clk_regmap c3_rtc_xtal_clkin = {
	.data = &(struct clk_regmap_gate_data) {
		.offset = RTC_BY_OSCIN_CTRL0,
		.bit_idx = 31,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_xtal_clkin",
		.ops = &clk_regmap_gate_ops,
		.parent_data = &(const struct clk_parent_data) {
			.fw_name = "oscin",
		},
		.num_parents = 1,
	},
};

static const struct meson_clk_dualdiv_param c3_rtc_32k_div_table[] = {
	{ 733, 732, 8, 11, 1 },
	{ /* sentinel */ }
};

static struct clk_regmap c3_rtc_32k_div = {
	.data = &(struct meson_clk_dualdiv_data) {
		.n1 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 0,
			.width   = 12,
		},
		.n2 = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 12,
			.width   = 12,
		},
		.m1 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 0,
			.width   = 12,
		},
		.m2 = {
			.reg_off = RTC_BY_OSCIN_CTRL1,
			.shift   = 12,
			.width   = 12,
		},
		.dual = {
			.reg_off = RTC_BY_OSCIN_CTRL0,
			.shift   = 28,
			.width   = 1,
		},
		.table = c3_rtc_32k_div_table,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_32k_div",
		.ops = &meson_clk_dualdiv_ops,
		.parent_hws = (const struct clk_hw *[]) {
			&c3_rtc_xtal_clkin.hw
		},
		.num_parents = 1,
	},
};

static const struct clk_parent_data c3_rtc_32k_parents[] = {
	{ .hw = &c3_rtc_32k_div.hw },
	{ .hw = &c3_rtc_xtal_clkin.hw }
};

static struct clk_regmap c3_rtc_32k_sel = {
	.data = &(struct clk_regmap_mux_data) {
		.offset = RTC_BY_OSCIN_CTRL1,
		.mask = 0x1,
		.shift = 24,
	},
	.hw.init = &(struct clk_init_data) {
		.name = "rtc_32k_sel",
		.