// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Intel Corporation
*
* Authors:
* Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
*
* Maintained by: <tpmdd-devel@lists.sourceforge.net>
*
* This device driver implements the TPM interface as defined in
* the TCG CRB 2.0 TPM specification.
*/
#include <linux/acpi.h>
#include <linux/highmem.h>
#include <linux/rculist.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#ifdef CONFIG_ARM64
#include <linux/arm-smccc.h>
#endif
#include "tpm_crb_ffa.h"
#include "tpm.h"
#define ACPI_SIG_TPM2 "TPM2"
#define TPM_CRB_MAX_RESOURCES 3
static const guid_t crb_acpi_start_guid =
GUID_INIT(0x6BBF6CAB, 0x5463, 0x4714,
0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4);
enum crb_defaults {
CRB_ACPI_START_REVISION_ID = 1,
CRB_ACPI_START_INDEX = 1,
};
enum crb_loc_ctrl {
CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0),
CRB_LOC_CTRL_RELINQUISH = BIT(1),
};
enum crb_loc_state {
CRB_LOC_STATE_LOC_ASSIGNED = BIT(1),
CRB_LOC_STATE_TPM_REG_VALID_STS = BIT(7),
};
enum crb_ctrl_req {
CRB_CTRL_REQ_CMD_READY = BIT(0),
CRB_CTRL_REQ_GO_IDLE = BIT(1),
};
enum crb_ctrl_sts {
CRB_CTRL_STS_ERROR = BIT(0),
CRB_CTRL_STS_TPM_IDLE = BIT(1),
};
enum crb_start {
CRB_START_INVOKE = BIT(0),
};
enum crb_cancel {
CRB_CANCEL_INVOKE = BIT(0),
};
struct crb_regs_head {
u32 loc_state;
u32 reserved1;
u32 loc_ctrl;
u32 loc_sts;
u8 reserved2[32];
u64 intf_id;
u64 ctrl_ext;
} __packed;
struct crb_regs_tail {
u32 ctrl_req;
u32 ctrl_sts;
u32 ctrl_cancel;
u32 ctrl_start;
u32 ctrl_int_enable;
u32 ctrl_int_sts;
u32 ctrl_cmd_size;
u32 ctrl_cmd_pa_low;
u32 ctrl_cmd_pa_high;
u32 ctrl_rsp_size;
u64 ctrl_rsp_pa;
} __packed;
enum crb_status {
CRB_DRV_STS_COMPLETE = BIT(0),
};
struct crb_priv {
u32 sm;
const char *hid;
struct crb_regs_head __iomem *regs_h;
struct crb_regs_tail __iomem *regs_t;
u8 __iomem *cmd;
u8 __iomem *rsp;
u32 cmd_size;
u32 smc_func_id;
u32 __iomem *pluton_start_addr;
u32 __iomem *pluton_reply_addr;
u8 ffa_flags;
u8 ffa_attributes;
};
struct tpm2_crb_smc {
u32 interrupt;
u8 interrupt_flags;
u8 op_flags;
u16 reserved2;
u32 smc_func_id;
};
/* CRB over FFA start method parameters in TCG2 ACPI table */
struct tpm2_crb_ffa {
u8 flags;
u8 attributes;
u16 partition_id;
u8 reserved[8];
};
struct tpm2_crb_pluton {
u64 start_addr;
u64 reply_addr;
};
/*
* Returns true if the start method supports idle.
*/
static inline bool tpm_crb_has_idle(u32 start_method)
{
return !(start_method == ACPI_TPM2_START_METHOD ||
start_method == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD ||
start_method == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC);
}
static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value,
unsigned long timeout)
{
ktime_t start;
ktime_t stop;
start = ktime_get();
stop = ktime_add(start, ms_to_ktime(timeout));
do {
if ((ioread32(reg) & mask) == value)
return true;
usleep_range(50, 100);
} while (ktime_before(ktime_get(), stop));
return ((ioread32(reg) & mask) == value);
}
static int crb_try_pluton_doorbell(struct crb_priv *priv, bool wait_for_complete)
{
if (priv->sm != ACPI_TPM2_COMMAND_BUFFER_WITH_PLUTON)
return 0;
if (!crb_wait_for_reg_32(priv->pluton_reply_addr, ~0, 1, TPM2_TIMEOUT_C))
return -ETIME;
iowrite32(1, priv->pluton_start_addr);
if (wait_for_complete == false)
return 0;
if (!crb_wait_for_reg_32(priv->pluton_start_addr,
0xffffffff, 0, 200))
return -ETIME;
return 0;
}
/**
* __crb_go_idle - request tpm crb device to go the idle state
*
* @dev: crb device
* @priv: crb private data
* @loc: locality
*
* Write CRB_CTRL_REQ_GO_IDLE to TPM_CRB_CTRL_REQ
* The device should respond within TIMEOUT_C by clearing the bit.
* Anyhow, we do not wait here as a consequent CMD_READY request
* will be handled correctly even if idle was not completed.
*
* The function does nothing for devices with ACPI-start method
* or SMC-start method.
*
* Return: 0 always
*/
static int __crb_go_idle(struct device *dev, struct crb_priv *priv, int loc)
{
int rc;
if (!tpm_crb_has_idle(priv->sm))