// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019, Intel Corporation.
*
* Heterogeneous Memory Attributes Table (HMAT) representation
*
* This program parses and reports the platform's HMAT tables, and registers
* the applicable attributes with the node's interfaces.
*/
#define pr_fmt(fmt) "acpi/hmat: " fmt
#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/list_sort.h>
#include <linux/memregion.h>
#include <linux/memory.h>
#include <linux/mutex.h>
#include <linux/node.h>
#include <linux/sysfs.h>
#include <linux/dax.h>
#include <linux/memory-tiers.h>
static u8 hmat_revision;
static int hmat_disable __initdata;
void __init disable_hmat(void)
{
hmat_disable = 1;
}
static LIST_HEAD(targets);
static LIST_HEAD(initiators);
static LIST_HEAD(localities);
static DEFINE_MUTEX(target_lock);
/*
* The defined enum order is used to prioritize attributes to break ties when
* selecting the best performing node.
*/
enum locality_types {
WRITE_LATENCY,
READ_LATENCY,
WRITE_BANDWIDTH,
READ_BANDWIDTH,
};
static struct memory_locality *localities_types[4];
struct target_cache {
struct list_head node;
struct node_cache_attrs cache_attrs;
};
enum {
NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL = ACCESS_COORDINATE_MAX,
NODE_ACCESS_CLASS_GENPORT_SINK_CPU,
NODE_ACCESS_CLASS_MAX,
};
struct memory_target {
struct list_head node;
unsigned int memory_pxm;
unsigned int processor_pxm;
struct resource memregions;
struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];
struct list_head caches;
struct node_cache_attrs cache_attrs;
u8 gen_port_device_handle[ACPI_SRAT_DEVICE_HANDLE_SIZE];
bool registered;
};
struct memory_initiator {
struct list_head node;
unsigned int processor_pxm;
bool has_cpu;
};
struct memory_locality {
struct list_head node;
struct acpi_hmat_locality *hmat_loc;
};
static struct memory_initiator *find_mem_initiator(unsigned int cpu_pxm)
{
struct memory_initiator *initiator;
list_for_each_entry(initiator, &initiators, node)
if (initiator->processor_pxm == cpu_pxm)
return initiator;
return NULL;
}
static struct memory_target *find_mem_target(unsigned int mem_pxm)
{
struct memory_target *target;
list_for_each_entry(target, &targets, node)
if (target->memory_pxm == mem_pxm)
return target;
return NULL;
}
/**
* hmat_get_extended_linear_cache_size - Retrieve the extended linear cache size
* @backing_res: resource from the backing media
* @nid: node id for the memory region
* @cache_size: (Output) size of extended linear cache.
*
* Return: 0 on success. Errno on failure.
*
*/
int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid,
resource_size_t *cache_size)
{
unsigned int pxm = node_to_pxm(nid);
struct memory_target *target;
struct target_cache *tcache;
struct resource *res;
target = find_mem_target(pxm);
if (!target)
return -ENOENT;
list_for_each_entry(tcache, &target->caches, node) {
if (tcache->cache_attrs.address_mode !=
NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR)
continue;
res = &target->memregions;
if (!resource_contains(res, backing_res))
continue;
*cache_size = tcache->cache_attrs.size;
return 0;
}
*cache_size = 0;
return 0;
}
EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, "CXL");
static struct memory_target *acpi_find_genport_target(u32 uid)
{
struct memory_target *target;
u32 target_uid;
u8 *uid_ptr;
list_for_each_entry(target