path: root/arch/arm64/boot/dts/exynos/exynos7870.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos7870 SoC device tree source
 *
 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
 * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
 */

#include <dt-bindings/clock/samsung,exynos7870-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos7870";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_dispaud;
		pinctrl2 = &pinctrl_ese;
		pinctrl3 = &pinctrl_fsys;
		pinctrl4 = &pinctrl_mif;
		pinctrl5 = &pinctrl_nfc;
		pinctrl6 = &pinctrl_top;
		pinctrl7 = &pinctrl_touch;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
		};
	};

	oscclk: oscclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend = <0xc4000001>;
		cpu_off = <0x84000002>;
		cpu_on = <0xc4000003>;
	};

	soc: soc@0 {
		compatible = "simple-bus";
		ranges = <0x0 0x0 0x0 0x20000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		chipid@10100000 {
			compatible = "samsung,exynos7870-chipid",
				     "samsung,exynos4210-chipid";
			reg = <0x10100000 0x100>;
		};

		cmu_peri: clock-controller@101f0000 {
			compatible = "samsung,exynos7870-cmu-peri";
			reg = <0x101f0000 0x1000>;
			#clock-cells = <1>;

			clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",
				      "spi3", "spi4", "uart0", "uart1", "uart2";
			clocks = <&oscclk>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
				 <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
		};

		cmu_mif: clock-controller@10460000 {
			compatible = "samsung,exynos7870-cmu-mif";
			reg = <0x10460000 0x1000>;
			#clock-cells = <1>;

			clock-names = "oscclk";
			clocks = <&oscclk>;
		};

		pmu_system_controller: system-controller@10480000 {
			compatible = "samsung,exynos7870-pmu",
				     "samsung,exynos7-pmu", "syscon";