path: root/arch/arm64/boot/dts/amlogic/meson-s4.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-s4-gpio.h>
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
#include <dt-bindings/power/meson-s4-power.h>
#include <dt-bindings/reset/amlogic,meson-s4-reset.h>

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	firmware {
		sm: secure-monitor {
			compatible = "amlogic,meson-gxbb-sm";

			pwrc: power-controller {
				compatible = "amlogic,meson-s4-pwrc";
				#power-domain-cells = <1>;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x2000>,
			      <0x0 0xfff04000 0 0x2000>,
			      <0x0 0xfff06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb4: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			clkc_periphs: clock-controller@0 {
				compatible = "amlogic,s4-peripherals-clkc";
				reg = <0x0 0x0 0x0 0x49c>;
				clocks = <&clkc_pll CLKID_FCLK_DIV2>,
					<&clkc_pll CLKID_FCLK_DIV2P5>,
					<&clkc_pll CLKID_FCLK_DIV3>,
					<&clkc_pll CLKID_FCLK_DIV4>,
					<&clkc_pll CLKID_FCLK_DIV5>,
					<&clkc_pll CLKID_FCLK_DIV7>,
					<&clkc_pll CLKID_HIFI_PLL>,
					<&clkc_pll CLKID_GP0_PLL>,
					<&clkc_pll CLKID_MPLL0>,
					<&clkc_pll CLKID_MPLL1>,
					<&clkc_pll CLKID_MPLL2>,
					<&clkc_pll CLKID_MPLL3>,
					<&clkc_pll CLKID_HDMI_PLL>,
					<&xtal>;
				clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",
						"fclk_div4", "fclk_div5", "fclk_div7",
						"hifi_pll", "gp0_pll", "mpll0", "mpll1",
						"mpll2", "mpll3", "hdmi_pll", "xtal";
				#clock-cells = <1>;
			};

			clkc_pll: clock-controller@8000 {
				compatible = "amlogic,s4-pll-clkc";
				reg = <0x0 0x8000 0x0 0x1e8>;
				clocks = <&xtal>;
				clock-names = "xtal";
				#clock-cells = <1>;
			};

			watchdog@2100 {
				compatible = "amlogic,s4-wdt", "amlogic,t7-wdt";
				reg = <0x0 0x2100 0x0 0x10>;
				clocks = <&xtal>;
			};

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,meson-s4-periphs-pinctrl";
				#address-cells = <2>