path: root/arch/arm/mm/cache.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * This file defines C prototypes for the low-level cache assembly functions
 * and populates a vtable for each selected ARM CPU cache type.
 */

#include <linux/types.h>
#include <asm/cacheflush.h>

#ifdef CONFIG_CPU_CACHE_V4
void v4_flush_icache_all(void);
void v4_flush_kern_cache_all(void);
void v4_flush_user_cache_all(void);
void v4_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4_coherent_kern_range(unsigned long, unsigned long);
int v4_coherent_user_range(unsigned long, unsigned long);
void v4_flush_kern_dcache_area(void *, size_t);
void v4_dma_map_area(const void *, size_t, int);
void v4_dma_unmap_area(const void *, size_t, int);
void v4_dma_flush_range(const void *, const void *);

struct cpu_cache_fns v4_cache_fns __initconst = {
	.flush_icache_all = v4_flush_icache_all,
	.flush_kern_all = v4_flush_kern_cache_all,
	.flush_kern_louis = v4_flush_kern_cache_all,
	.flush_user_all = v4_flush_user_cache_all,
	.flush_user_range = v4_flush_user_cache_range,
	.coherent_kern_range = v4_coherent_kern_range,
	.coherent_user_range = v4_coherent_user_range,
	.flush_kern_dcache_area = v4_flush_kern_dcache_area,
	.dma_map_area = v4_dma_map_area,
	.dma_unmap_area = v4_dma_unmap_area,
	.dma_flush_range = v4_dma_flush_range,
};
#endif

/* V4 write-back cache "V4WB" */
#ifdef CONFIG_CPU_CACHE_V4WB
void v4wb_flush_icache_all(void);
void v4wb_flush_kern_cache_all(void);
void v4wb_flush_user_cache_all(void);
void v4wb_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4wb_coherent_kern_range(unsigned long, unsigned long);
int v4wb_coherent_user_range(unsigned long, unsigned long);
void v4wb_flush_kern_dcache_area(void *, size_t);
void v4wb_dma_map_area(const void *, size_t, int);
void v4wb_dma_unmap_area(const void *, size_t, int);
void v4wb_dma_flush_range(const void *, const void *);

struct cpu_cache_fns v4wb_cache_fns __initconst = {
	.flush_icache_all = v4wb_flush_icache_all,
	.flush_kern_all = v4wb_flush_kern_cache_all,
	.flush_kern_louis = v4wb_flush_kern_cache_all,
	.flush_user_all = v4wb_flush_user_cache_all,
	.flush_user_range = v4wb_flush_user_cache_range,
	.coherent_kern_range = v4wb_coherent_kern_range,
	.coherent_user_range = v4wb_coherent_user_range,
	.flush_kern_dcache_area = v4wb_flush_kern_dcache_area,
	.dma_map_area = v4wb_dma_map_area,
	.dma_unmap_area = v4wb_dma_unmap_area,
	.dma_flush_range = v4wb_dma_flush_range,
};
#endif

/* V4 write-through cache "V4WT" */
#ifdef CONFIG_CPU_CACHE_V4WT
void v4wt_flush_icache_all(void);
void v4wt_flush_kern_cache_all(void);
void v4wt_flush_user_cache_all(void);
void v4wt_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v4wt_coherent_kern_range(unsigned long, unsigned long);
int v4wt_coherent_user_range(unsigned long, unsigned long);
void v4wt_flush_kern_dcache_area(void *, size_t);
void v4wt_dma_map_area(const void *, size_t, int);
void v4wt_dma_unmap_area(const void *, size_t, int);
void v4wt_dma_flush_range(const void *, const void *);

struct cpu_cache_fns v4wt_cache_fns __initconst = {
	.flush_icache_all = v4wt_flush_icache_all,
	.flush_kern_all = v4wt_flush_kern_cache_all,
	.flush_kern_louis = v4wt_flush_kern_cache_all,
	.flush_user_all = v4wt_flush_user_cache_all,
	.flush_user_range = v4wt_flush_user_cache_range,
	.coherent_kern_range = v4wt_coherent_kern_range,
	.coherent_user_range = v4wt_coherent_user_range,
	.flush_kern_dcache_area = v4wt_flush_kern_dcache_area,
	.dma_map_area = v4wt_dma_map_area,
	.dma_unmap_area = v4wt_dma_unmap_area,
	.dma_flush_range = v4wt_dma_flush_range,
};
#endif

/* Faraday FA526 cache */
#ifdef CONFIG_CPU_CACHE_FA
void fa_flush_icache_all(void);
void fa_flush_kern_cache_all(void);
void fa_flush_user_cache_all(void);
void fa_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void fa_coherent_kern_range(unsigned long, unsigned long);
int fa_coherent_user_range(unsigned long, unsigned long);
void fa_flush_kern_dcache_area(void *, size_t);
void fa_dma_map_area(const void *, size_t, int);
void fa_dma_unmap_area(const void *, size_t, int);
void fa_dma_flush_range(const void *, const void *);

struct cpu_cache_fns fa_cache_fns __initconst = {
	.flush_icache_all = fa_flush_icache_all,
	.flush_kern_all = fa_flush_kern_cache_all,
	.flush_kern_louis = fa_flush_kern_cache_all,
	.flush_user_all = fa_flush_user_cache_all,
	.flush_user_range = fa_flush_user_cache_range,
	.coherent_kern_range = fa_coherent_kern_range,
	.coherent_user_range = fa_coherent_user_range,
	.flush_kern_dcache_area = fa_flush_kern_dcache_area,
	.dma_map_area = fa_dma_map_area,
	.dma_unmap_area = fa_dma_unmap_area,
	.dma_flush_range = fa_dma_flush_range,
};
#endif

#ifdef CONFIG_CPU_CACHE_V6
void v6_flush_icache_all(void);
void v6_flush_kern_cache_all(void);
void v6_flush_user_cache_all(void);
void v6_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v6_coherent_kern_range(unsigned long, unsigned long);
int v6_coherent_user_range(unsigned long, unsigned long);
void v6_flush_kern_dcache_area(void *, size_t);
void v6_dma_map_area(const void *, size_t, int);
void v6_dma_unmap_area(const void *, size_t, int);
void v6_dma_flush_range(const void *, const void *);

struct cpu_cache_fns v6_cache_fns __initconst = {
	.flush_icache_all = v6_flush_icache_all,
	.flush_kern_all = v6_flush_kern_cache_all,
	.flush_kern_louis = v6_flush_kern_cache_all,
	.flush_user_all = v6_flush_user_cache_all,
	.flush_user_range = v6_flush_user_cache_range,
	.coherent_kern_range = v6_coherent_kern_range,
	.coherent_user_range = v6_coherent_user_range,
	.flush_kern_dcache_area = v6_flush_kern_dcache_area,
	.dma_map_area = v6_dma_map_area,
	.dma_unmap_area = v6_dma_unmap_area,
	.dma_flush_range = v6_dma_flush_range,
};
#endif

#ifdef CONFIG_CPU_CACHE_V7
void v7_flush_icache_all(void);
void v7_flush_kern_cache_all(void);
void v7_flush_kern_cache_louis(void);
void v7_flush_user_cache_all(void);
void v7_flush_user_cache_range(unsigned long, unsigned long, unsigned int);
void v7_coherent_kern_range(un