path: root/arch/arm/boot/dts/rockchip/rk3066a.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include <dt-bindings/power/rk3066-power.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	aliases {
		gpio4 = &gpio4;
		gpio6 = &gpio6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points =
				/* kHz    uV */
				<1416000 1300000>,
				<1200000 1175000>,
				<1008000 1125000>,
				<816000  1125000>,
				<600000  1100000>,
				<504000  1100000>,
				<312000  1075000>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop0_out>, <&vop1_out>;
	};

	hdmi_sound: hdmi-sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "HDMI";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <256>;
		status = "disabled";

		simple-audio-card,codec {
			sound-dai = <&hdmi>;
		};

		simple-audio-card,cpu {
			sound-dai = <&i2s0>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	vop0: vop@1010c000 {
		compatible = "rockchip,rk3066-vop";
		reg = <0x1010c000 0x19c>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC0>,
			 <&cru DCLK_LCDC0>,
			 <&cru HCLK_LCDC0>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3066_PD_VIO>;
		resets = <&cru SRST_LCDC0_AXI>,
			 <&cru SRST_LCDC0_AHB>,
			 <&cru SRST_LCDC0_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vop0_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vop0_out_hdmi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hdmi_in_vop0>;
			};
		};
	};

	vop1: vop@1010e000 {
		compatible = "rockchip,rk3066-vop";
		reg = <0x1010e000 0x19c>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC1>,
			 <&cru DCLK_LCDC1>,
			 <&cru HCLK_LCDC1>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <&power RK3066_PD_VIO>;
		resets = <&cru SRST_LCDC1_AXI>,
			 <&cru SRST_LCDC1_AHB>,
			 <&cru SRST_LCDC1_DCLK>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vop1_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vop1_out_hdmi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hdmi_in_vop1>;
			};
		};
	};

	hdmi: hdmi@10116000 {
		compatible = "rockchip,rk3066-hdmi";
		reg = <0x10116000 0x2000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HDMI>;
		clock-names = "hclk";
		pinctrl-names = "default";
		pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
		power-domains = <&power RK3066_PD_VIO>;
		rockchip,grf = <&grf></