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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Verisilicon DC-series display controllers
maintainers:
- Icenowy Zheng <uwu@icenowy.me>
properties:
$nodename:
pattern: "^display@[0-9a-f]+$"
compatible:
items:
- enum:
- thead,th1520-dc8200
- const: verisilicon,dc # DC IPs have discoverable ID/revision registers
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: DC Core clock
- description: DMA AXI bus clock
- description: Configuration AHB bus clock
- description: Pixel clock of output 0
- description: Pixel clock of output 1
clock-names:
items:
- const: core
- const: axi
- const: ahb
- const: pix0
- const: pix1
resets:
items:
- description: DC Core reset
- description: DMA AXI bus reset
- description: Configuration AHB bus reset
reset-names:
items:
- const: core
- const: axi
- const: ahb
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The first output channel , endpoint 0 should be
used for DPI format output and endpoint 1 should be used
for DP format output.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: The second output channel if the DC variant
supports. Follow the same endpoint addressing rule with
the first port.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
#include <dt-bindings/reset/thead,th1520-reset.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
display@ffef600000 {
compatible = "thead,th1520-dc8200", "verisilicon,dc";
reg = <0xff 0xef600000 0x0 0x100000>;
interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_DPU_CCLK>,
<&clk_vo CLK_DPU_ACLK>,
<&clk_vo CLK_DPU_HCLK>,
<&clk_vo CLK_DPU_PIXELCLK0>,
<&clk_vo CLK_DPU_PIXELCLK1>;
clock-names = "core", "axi", "ahb", "pix0", "pix1";
resets = <&rst TH1520_RESET_ID_DPU_CORE>,
<&rst TH1520_RESET_ID_DPU_AXI>,
<&rst TH1520_RESET_ID_DPU_AHB>;
reset-names = "core", "axi", "ahb";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dpu_out_dp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
|
