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path: root/tools/testing/cxl/test/mock.c
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2025-11-18Merge branch 'for-6.19/cxl-misc' into cxl-for-nextDave Jiang1-17/+0
2025-11-18cxl/test: remove unused mock function for cxl_rcd_component_reg_phys()Alejandro Lucero1-17/+0
2025-11-17Merge branch 'for-6.19/cxl-elc-test' into cxl-for-nextDave Jiang1-0/+20
2025-11-17cxl/test: Add support for acpi extended linear cacheDave Jiang1-0/+20
2025-11-03cxl/port: Remove devm_cxl_port_enumerate_dports()Li Ming1-15/+0
2025-09-18cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()Dave Jiang1-3/+7
2025-09-18cxl/test: Add mock version of devm_cxl_add_dport_by_dev()Dave Jiang1-0/+23
2025-09-18cxl/test: Refactor decoder setup to reduce cxl_test burdenDave Jiang1-61/+8
2025-05-06cxl/test: Address missing MODULE_DESCRIPTION warnings for cxl_testDave Jiang1-0/+1
2025-01-02cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()Alejandro Lucero1-3/+3
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra1-14/+14
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-2/+2
2024-09-03cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming1-3/+3
2024-08-09cxl/test: Skip cxl_setup_parent_dport() for emulated dportsLi Ming1-0/+12
2024-02-16cxl/test: Add support for qos_class checkingDave Jiang1-0/+14
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-11/+33
2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-15/+0
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-5/+5
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-1/+3
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-7/+27
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-0/+15
2023-05-13tools/testing/cxl: Use DEFINE_STATIC_SRCU()Dan Williams1-1/+1
2023-02-14cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-3/+5
2023-02-14cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-3/+4
2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang1-2/+19
2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter1-0/+19
2022-06-28tools/testing/cxl: Fix cxl_hdm_decode_init() calling conventionDan Williams1-3/+5
2022-05-19cxl/port: Reuse 'struct cxl_hdm' context for hdm initDan Williams1-2/+3
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams1-6/+3
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams1-4/+4
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-0/+16
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-0/+15
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-16/+12
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-0/+50
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams1-26/+19
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-21/+9
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-0/+171
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