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2026-01-15ACPICA: Refactor for TPR Base/Limit registers bitmasksMichal Camacho Romero1-140/+256
Link: https://github.com/acpica/acpica/commit/5cb62a1d4970 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3193976.CbtlEUcBR6@rafael.j.wysocki
2026-01-15ACPICA: Replace TPRn Base and Limit registersMichal Camacho Romero1-27/+72
Replace TPRn Base and Limit registers with compatible bitmasks for them. Link: https://github.com/acpica/acpica/commit/be91c5813936 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki
2026-01-15ACPICA: Align comments in TPRn-related structuresMichal Camacho Romero1-16/+14
Align comments in ACPI_TPRN_BASE_REG and ACPI_TPRN_LIMIT_REG structures. Link: https://github.com/acpica/acpica/commit/95815d550969 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2286538.NgBsaNRSFp@rafael.j.wysocki
2026-01-15ACPICA: Cleanup comments and DTPR Table handle functionsMichal Camacho Romero1-17/+18
Link: https://github.com/acpica/acpica/commit/cc480264335e Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2042656.yKVeVyVuyW@rafael.j.wysocki
2026-01-15ACPICA: Verify DTPR and TPR Instance buffer pointersMichal Camacho Romero1-27/+32
Verify DTPR and TPR Instance buffer pointers and refactor comments. Link: https://github.com/acpica/acpica/commit/bdec5b61cf5b Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/884204745.0ifERbkFSE@rafael.j.wysocki
2026-01-15ACPICA: Fix Segmentation Fault error related to DTPRMichal Camacho Romero1-5/+5
Fix Segmentation Fault error, caused by invalid buffer lenght in DTPR Table Template: * Update buffer length for TPR Table, which invalid value caused Segmentation Fault, during ASL file production. * Refactor invalid values of TPR instances, arrays and serialization requests count and TPR Base addresses in the DTPR table template. * Fix offset updating in the acpi_dm_dump_dtpr function. Link: https://github.com/acpica/acpica/commit/f75850bc4717 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2541195.jE0xQCEvom@rafael.j.wysocki
2026-01-15ACPICA: Create auxiliary ACPI_TPR_AUX_SR structure for iASL compilerMichal Camacho Romero1-0/+5
Define unofficial structure ACPI_TPR_AUX_SR, which holds information about the number of serialization registers for TPRs. It simplifies DTPR Serialization Request Info Table compilation. Link: https://github.com/acpica/acpica/commit/31f470e708a9 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2266165.Icojqenx9y@rafael.j.wysocki
2026-01-15ACPICA: Define DTPR structure related info tables and data templateMichal Camacho Romero1-1/+2
* DTPR Table Info * TPR Instance Table Info * TPR Array Table Info * TPR Serialize Request Table Info * DTPR Table Data Template Link: https://github.com/acpica/acpica/commit/abadf1d34732 Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3676546.iIbC2pHGDl@rafael.j.wysocki
2026-01-15ACPICA: Add DTPR table support for the ASL compilerMichal Camacho Romero1-4/+4
Define DTPR related structures offsets. Link: https://github.com/acpica/acpica/commit/c6fc16c8936d Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/7902293.EvYhyI6sBW@rafael.j.wysocki
2026-01-15ACPICA: Add support for the new ACPI Table: DTPRMichal Camacho Romero1-0/+86
Define a new the ACPI Table, structure and registers, related with it, according to the latest version of the Intel TXT DMA Protection Ranges (TPR) specification (Revision 0.73): * DTPR ACPI Table * TPR Base Register * TPR Serialize Request Register * TPR Limit Register * TPR Instance Structure * DMAR TXT Protected Reporting Structure These structures will be used to handle TPRs on the Intel CPU's. Link: https://github.com/acpica/acpica/commit/10e7a88f70da Link: https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/6234415.lOV4Wx5bFT@rafael.j.wysocki
2025-10-04Merge tag 'cxl-for-6.18' of ↵Linus Torvalds1-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl Pull CXL updates from Dave Jiang: "The changes include adding poison injection support, fixing CXL access coordinates when onlining CXL memory, and delaing the enumeration of downstream switch ports for CXL hierarchy to ensure that the CXL link is established at the time of enumeration to address a few issues observed on AMD and Intel platforms. Misc changes: - Use str_plural() instead of open code for emitting strings. - Use str_enabled_disabled() instead of ternary operator - Fix emit of type resource_size_t argument for validate_region_offset() - Typo fixup in CXL driver-api documentation - Rename CFMWS coherency restriction defines - Add convention doc describe dealing with x86 low memory hole and CXL Poison Inject support: - Move hpa_to_spa callback to new reoot decoder ops structure - Define a SPA to HPA callback for interleave calculation with XOR math - Add support for SPA to DPA address translation with XOR - Add locked variants of poison inject and clear functions - Add inject and clear poison support by region offset CXL access coordinates update fix: - A comment update for hotplug memory callback prority defines - Add node_update_perf_attrs() for updating perf attrs on a node - Update cxl_access_coordinates() to use the new node update function - Remove hmat_update_target_coordinates() and related code CXL delayed downstream port enumeration and initialization: - Add helper to detect top of CXL device topology and remove open coding - Add helper to delete single dport - Add a cached copy of target_map to cxl_decoder - Refactor decoder setup to reduce cxl_test burden - Defer dport allocation for switch ports - Add mock version of devm_cxl_add_dport_by_dev() for cxl_test - Adjust the mock version of devm_cxl_switch_port_decoders_setup() due to cxl core usage - Setup target_map for cxl_test decoder initialization - Change SSLBIS handler to handle single dport - Move port register setup to when first dport appears" * tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits) cxl: Move port register setup to when first dport appear cxl: Change sslbis handler to only handle single dport cxl/test: Setup target_map for cxl_test decoder initialization cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup() cxl/test: Add mock version of devm_cxl_add_dport_by_dev() cxl: Defer dport allocation for switch ports cxl/test: Refactor decoder setup to reduce cxl_test burden cxl: Add a cached copy of target_map to cxl_decoder cxl: Add helper to delete dport cxl: Add helper to detect top of CXL device topology cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution cxl/acpi: Rename CFMW coherency restrictions Documentation/driver-api: Fix typo error in cxl acpi/hmat: Remove now unused hmat_update_target_coordinates() cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT drivers/base/node: Add a helper function node_update_perf_attrs() mm/memory_hotplug: Update comment for hotplug memory callback priorities cxl: Fix emit of type resource_size_t argument for validate_region_offset() cxl/region: Add inject and clear poison by region offset cxl/core: Add locked variants of the poison inject and clear funcs ...
2025-09-15ACPICA: CEDT: Add Back-Invalidate restriction to CXL WindowDavidlohr Bueso1-0/+1
This is added in newer version (3.0+) of the CXL Spec to support the HDM-DB coherency model. Link: https://github.com/acpica/acpica/commit/a6886da1 Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-10cxl/acpi: Rename CFMW coherency restrictionsDavidlohr Bueso1-2/+2
ACPICA commit 710745713ad3a2543dbfb70e84764f31f0e46bdc This has been renamed in more recent CXL specs, as type3 (memory expanders) can also use HDM-DB for device coherent memory. Link: https://github.com/acpica/acpica/commit/710745713ad3a2543dbfb70e84764f31f0e46bdc Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250908160034.86471-1-dave@stgolabs.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-12ACPICA: Update copyright yearSaket Dumbre1-1/+1
ACPICA commit 45253be18b3f37d46cd0072aa3f8a0a21a70e0a4 Changes needed by acpisrc to update copyright year when building for release. Link: https://github.com/acpica/acpica/commit/45253be1 Signed-off-by: Saket Dumbre <saket.dumbre@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-05-12ACPICA: infrastructure: Add new DMT_BUF types and shorten a long nameTony Luck1-1/+1
ACPICA commit b8713f71b4023a0396fe61503bbbf5226e5eed1b Some ERDT subtables have 11 and 24 byte reserved fields. Add the ACPI_DMT_BUF11 and ACPI_DMT_BUF24 types to describe these reserved fields in struct acpi_dmtable_info structures. Shorten the ACPI_SUBTABLE_HEADER_16 name to ACPI_SUBTBL_HDR Link: https://github.com/acpica/acpica/commit/b8713f71 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3643286.iIbC2pHGDl@rjwysocki.net
2025-05-12ACPICA: infrastructure: Add new header and ACPI_DMT_BUF26 typesTony Luck1-0/+7
ACPICA commit 52840d3826bd7e183fcb555e044e190aea0b5021 New MRRM tables can have subtables that are larger than 255 bytes. Add a new header typedef that uses u16 for Length. Could be backported to acpi_aspt_header, struct acpi_dmar_header, struct acpi_nfit_header, struct acpi_prmt_module_header, struct acpi_prmt_module_info. Will be used for upcoming ERDT table. MRRM table has a 26-byte reserved section in header. Add ACPI_DMT_BUF26 to describe this in struct acpi_dmtable_info. Link: https://github.com/acpica/acpica/commit/52840d38 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3005638.e9J7NaK4W3@rjwysocki.net
2025-05-12ACPICA: Interpret SIDP structures in DMARAlexey Neyman1-2/+13
ACPICA commit af51f730e0bccf789686cea68e116d5f0b27aacb Added in revision 3.4 of the VT-d spec. To support SIDP, part of the previously reserved field in the device scope structure was used to create a 1-byte "Flags" field. Link: https://github.com/acpica/acpica/commit/af51f730 Signed-off-by: Alexey Neyman <aneyman@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2239745.irdbgypaU6@rjwysocki.net
2025-03-27ACPICA: actbl1: Add EINJv2 get error type actionZaid Alali1-1/+2
ACPICA commit 6975cd07e20ba955556e1eafe8a326834c354ae6 Add EINJV2_GET_ERROR_TYPE as defined in the new specs(1)(2). Link: https://bugzilla.tianocore.org/show_bug.cgi?id=4615 (1) Link: https://bugzilla.tianocore.org/attachment.cgi?id=1446 (2) Link: https://github.com/acpica/acpica/commit/6975cd07 Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3344273.aeNJFYEL58@rjwysocki.net
2025-03-27ACPICA: actbl1: Update values to hex to follow ACPI specsZaid Alali1-11/+11
ACPICA commit 0b44ed75fb551bf3fbbbd39ca72bd932872fff20 ACPI specs(1) define Error Injection Actions in hex values. This commit intends to update values from decimal to hex to be consistent with ACPI specs. Link: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html (1) Link: https://github.com/acpica/acpica/commit/0b44ed75 Signed-off-by: Zaid Alali <zaidal@os.amperecomputing.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/13729719.uLZWGnKmhe@rjwysocki.net
2024-11-08ACPI/CDAT: Add CDAT/DSMAS shared and read only flag valuesIra Weiny1-0/+2
The Coherent Device Attribute Table (CDAT) Device Scoped Memory Affinity Structure (DSMAS) version 1.04 [1] defines flags to indicate if a DPA range is read only and/or shared. Add read only and shareable flag definitions. This change was merged in ACPICA via PR 976.[2] Link: https://uefi.org/sites/default/files/resources/Coherent%20Device%20Attribute%20Table_1.04%20published_0.pdf [1] Link: https://github.com/acpica/acpica/pull/976 [2] Cc: Robert Moore <robert.moore@intel.com> Cc: Len Brown <lenb@kernel.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: linux-acpi@vger.kernel.org Cc: acpica-devel@lists.linux.dev Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20241107-dcd-type2-upstream-v7-2-56a84e66bc36@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2024-08-29ACPICA: HMAT: Add extended linear address mode to MSCISDave Jiang1-1/+4
ACPICA commit aaa08569b81aa4d9ff59f91f00e589e98d499e6c Redefine the 2 reserved bytes at offset 28 of Memory Side Cache Information Structure as "Address Mode" and add defines of the new value. * 0 - Reserved (Unkown Address Mode) * 1 - Extended-linear (N direct-map aliases linearly mapped) * 2..65535 - Reserved (Unknown Address Mode) Link: https://github.com/acpica/acpica/commit/aaa08569 Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-08-29ACPICA: Headers: Add RISC-V SBI Subtype to DBG2Sia Jee Heng1-0/+1
ACPICA commit 6f4c900bcf9ca065129353f17a83773aa58095aa Include the RISC-V SBI debugging subtype as documented in DBG2 dated April 10, 2023 [1]. Link: https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table # [1] Link: https://github.com/acpica/acpica/commit/6f4c900b Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-08-29ACPICA: Complete CXL 3.0 CXIMS structuresZhang Rui1-0/+4
ACPICA commit eb2a2ff303416fb3f6c425d519dbcd6988dbd91f Commit 2d8dc0383d3c9 ("Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table") introduces basic support for CXL XOR Interleave Math Structure (CXIMS). Complete the CXIMS structures. No functional change. Link: https://github.com/acpica/acpica/commit/eb2a2ff3 Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-04-12ACPICA: Fix CXL 3.0 structure (RDPAS) in the CEDT tableHojin Nam1-2/+0
ACPICA commit a0ad1ed5105fb8a15f6f8384b8ab0a2157efaf23 struct acpi_cedt_rdpas does not match with CXL r3.0 9.17.1.5 Table 9-24. reserved1 and length fields are already added by struct acpi_cedt_header. Link: https://github.com/acpica/acpica/commit/a0ad1ed5 Signed-off-by: Hojin Nam <hj96.nam@samsung.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-04-12ACPICA: actbl1.h: Add EINJ CXL error typesBen Cheatham1-0/+6
ACPICA commit c7171588a9f684afafc83c6c18ed0bab9274e5e6 Add EINJ CXL error types added in ACPI v6.5. Link: https://github.com/acpica/acpica/commit/c7171588 Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-10-03ACPICA: Add defines for CDAT SSLBISDave Jiang1-0/+3
Add upstream port and any port definition for SSLBIS. Link: https://github.com/acpica/acpica/pull/898 Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-07-10ACPICA: Fix misspelled CDAT DSMAS defineDave Jiang1-1/+1
ACPICA commit 32a50922b66a9e288b9a9b4740de86a542668a43 ACPI_CEDT_DSMAS_NON_VOLATILE -> ACPI_CDAT_DSMAS_NON_VOLATILE Link: https://github.com/acpica/acpica/commit/32a50922 Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: acpi_dmar_andd: Replace 1-element array with flexible arrayKees Cook1-1/+4
ACPICA commit 3c19ae70424e9ab1e1b805203d300d2660f9a2f7 Similar to "Replace one-element array with flexible-array", replace the 1-element array with a proper flexible array member as defined by C99. This allows the code to operate without tripping compile-time and run- time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds, and/or -fstrict-flex-arrays=3). The handling of struct acpi_dmar_andd by acpi_dm_dump_dmar() appears to expect a single trailing char for calculating table offsets. Keep a char in the union to avoid any code changes appearing in the .text or .data sections. Link: https://github.com/acpica/acpica/commit/3c19ae70 Signed-off-by: Kees Cook <kees@outflux.net> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: actbl1: Replace 1-element arrays with flexible arraysKees Cook1-3/+3
ACPICA commit 8c9bd5d151f77767b2fd937911848b7159dc8ee9 Similar to "Replace one-element array with flexible-array", replace the 1-element array with a proper flexible array member as defined by C99. This allows the code to operate without tripping compile-time and run- time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds, and/or -fstrict-flex-arrays=3). No .text nor .data differences result from this change. Link: https://github.com/acpica/acpica/commit/8c9bd5d1 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Update all copyrights/signons to 2023Bob Moore1-1/+1
ACPICA commit 25bddd1824b1e450829468a64bbdcb38074ba3d2 Copyright updates to 2023. Link: https://github.com/acpica/acpica/commit/25bddd18 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Add support for ASPT table in disassemblerJeremi Piotrowski1-0/+46
ACPICA commit 6771f8b758299bd383bab145d5fd36ec229b2d70 ASPT is the AMD Secure Processor table, found in Hyper-V VMs when SNP isolation is exposed to the VM and in some high-end AMD servers. This commit adds support for rev 1 of the ASPT spec in the disassembler. Link: https://github.com/acpica/acpica/commit/6771f8b7 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-24Merge tag 'iommu-updates-v6.3' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - Consolidate iommu_map/unmap functions. There have been blocking and atomic variants so far, but that was problematic as this approach does not scale with required new variants which just differ in the GFP flags used. So Jason consolidated this back into single functions that take a GFP parameter. - Retire the detach_dev() call-back in iommu_ops - Arm SMMU updates from Will: - Device-tree binding updates: - Cater for three power domains on SM6375 - Document existing compatible strings for Qualcomm SoCs - Tighten up clocks description for platform-specific compatible strings - Enable Qualcomm workarounds for some additional platforms that need them - Intel VT-d updates from Lu Baolu: - Add Intel IOMMU performance monitoring support - Set No Execute Enable bit in PASID table entry - Two performance optimizations - Fix PASID directory pointer coherency - Fix missed rollbacks in error path - Cleanups - Apple t8110 DART support - Exynos IOMMU: - Implement better fault handling - Error handling fixes - Renesas IPMMU: - Add device tree bindings for r8a779g0 - AMD IOMMU: - Various fixes for handling on SNP-enabled systems and handling of faults with unknown request-ids - Cleanups and other small fixes - Various other smaller fixes and cleanups * tag 'iommu-updates-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (71 commits) iommu/amd: Skip attach device domain is same as new domain iommu: Attach device group to old domain in error path iommu/vt-d: Allow to use flush-queue when first level is default iommu/vt-d: Fix PASID directory pointer coherency iommu/vt-d: Avoid superfluous IOTLB tracking in lazy mode iommu/vt-d: Fix error handling in sva enable/disable paths iommu/amd: Improve page fault error reporting iommu/amd: Do not identity map v2 capable device when snp is enabled iommu: Fix error unwind in iommu_group_alloc() iommu/of: mark an unused function as __maybe_unused iommu: dart: DART_T8110_ERROR range should be 0 to 5 iommu/vt-d: Enable IOMMU perfmon support iommu/vt-d: Add IOMMU perfmon overflow handler support iommu/vt-d: Support cpumask for IOMMU perfmon iommu/vt-d: Add IOMMU perfmon support iommu/vt-d: Support Enhanced Command Interface iommu/vt-d: Retrieve IOMMU perfmon capability information iommu/vt-d: Support size of the register set in DRHD iommu/vt-d: Set No Execute Enable bit in PASID table entry iommu/vt-d: Remove sva from intel_svm_dev ...
2023-02-15Merge branches 'acpi-processor', 'acpi-tables', 'acpi-pnp' and ↵Rafael J. Wysocki1-0/+2
'acpi-maintainers' Merge ACPI processor driver changes, ACPI table parser changes, ACPI device enumeration changes related to PNP and a MAINTAINERS update related to ACPI for 6.3-rc1: - Drop an unnecessary (void *) conversion from the ACPI processor driver (Zhou jie). - Modify the ACPI processor performance library code to use the "no limit" frequency QoS as appropriate and adjust the intel_pstate driver accordingly (Rafael Wysocki). - Add support for NBFT to the ACPI table parser (Stuart Hayes). - Introduce list of known non-PNP devices to avoid enumerating some of them as PNP devices (Rafael Wysocki). - Add x86 ACPI paths to the ACPI entry in MAINTAINERS to allow scripts to report the actual maintainers information (Rafael Wysocki). * acpi-processor: cpufreq: intel_pstate: Drop ACPI _PSS states table patching ACPI: processor: perflib: Avoid updating frequency QoS unnecessarily ACPI: processor: perflib: Use the "no limit" frequency QoS ACPI: processor: idle: Drop unnecessary (void *) conversion * acpi-tables: ACPI: tables: Add support for NBFT * acpi-pnp: ACPI: PNP: Introduce list of known non-PNP devices * acpi-maintainers: MAINTAINERS: Add x86 ACPI paths to the ACPI entry
2023-02-13ACPICA: Fix typo in CDAT DSMAS struct definitionLukas Wunner1-1/+1
ACPICA commit 9d8bd58d5f3495ce76d1b9767ec0b92251cbc366 Link: https://github.com/acpica/acpica/commit/9d8bd58d5f34 Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-03iommu/vt-d: Support size of the register set in DRHDKan Liang1-1/+1
A new field, which indicates the size of the remapping hardware register set for this remapping unit, is introduced in the DMA-remapping hardware unit definition (DRHD) structure with the VT-d Spec 4.0. With this information, SW doesn't need to 'guess' the size of the register set anymore. Update the struct acpi_dmar_hardware_unit to reflect the field. Store the size of the register set in struct dmar_drhd_unit for each dmar device. The 'size' information is ResvZ for the old BIOS and platforms. Fall back to the old guessing method. There is nothing changed. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Link: https://lore.kernel.org/r/20230128200428.1459118-2-kan.liang@linux.intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2022-12-30ACPI: tables: Add support for NBFTStuart Hayes1-0/+2
Add support for the NVMe Boot Firmware Table (NBFT) to facilitate booting from NVM Express namespaces which are accessed via NVMe over Fabrics (NVMe-oF). Signed-off-by: Stuart Hayes <stuart.w.hayes@gmail.com> Reviewed-by: John Meneghini <jmeneghi@redhat.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: Finish support for the CDAT tableBob Moore1-1/+115
ACPICA commit 8ac4e5116f59d6f9ba2fbeb9ce22ab58237a278f Finish support for the CDAT table, in both the data table compiler and the disassembler. Link: https://github.com/acpica/acpica/commit/8ac4e511 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT tableAlison Schofield1-1/+34
ACPICA commit 2d8dc0383d3c908389053afbdc329bbd52f009ce The CXL 3.0 Specification [1] adds two new structures to the CXL Early Discovery Table (CEDT). The CEDT may include zero or more entries of these types: CXIMS: CXL XOR Interleave Math Structure Enables the host to find a targets position in an Interleave Target List when XOR Math is used. RDPAS: RCEC Downstream Post Association Structure Enables the host to locate the Downstream Port(s) that report errors to a given Root Complex Event Collector (RCEC). Link: https://www.computeexpresslink.org/spec-landing # [1] Link: https://github.com/acpica/acpica/commit/2d8dc038 Signed-off-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Removed some tabs and // commentsBob Moore1-6/+6
ACPICA commit 0914618b553d6f3366e568409cebf2656891ca69 Automated cleanup; No functional changes. Link: https://github.com/acpica/acpica/commit/0914618b Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Update copyright notices to the year 2022Bob Moore1-1/+1
ACPICA commit 738d7b0726e6c0458ef93c0a01c0377490888d1e Affects all source modules and utility signons. Link: https://github.com/acpica/acpica/commit/738d7b07 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Add the subtable CFMWS to the CEDT tableLawrence Hileman1-0/+4
ACPICA commit 19b11f91660b1a38a8e9655b0b1a4ad51ec4db1e Link: https://github.com/acpica/acpica/commit/19b11f91 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-08-16ACPICA: Headers: Add new DBG2 Serial Port SubtypesMarcin Wojtas1-1/+14
The Microsoft Debug Port Table 2 (DBG2) specification revision September 21, 2020 comprises additional Serial Port Subtypes [1]. Reflect that in the actbl1.h header file. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table ACPICA commit d95c7d206b5836c7770e8e9cd613859887fded8f Link: https://github.com/acpica/acpica/commit/d95c7d20 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-08-16ACPICA: iASL: Add support for the AEST table (data compiler)Bob Moore1-0/+1
Includes support in the table compiler and the disassembler. ACPICA commit e75074d84d1207339a048486c2d06ecb935d0092 Link: https://github.com/acpica/acpica/commit/e75074d8 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-07ACPICA: Add the CFMWS structure definition to the CEDT tableAlison Schofield1-1/+30
ACPICA commit 699fc72e56936bebf3b9ba39b6e91bd957b44452 The CXL Fixed Memory Window Structure (CFMWS) is added to the CXL Early Discovery Table (CEDT). This new structure is defined in an ECN to the CXL 2.0 specification. https://www.computeexpresslink.org/spec-landing Link: https://github.com/acpica/acpica/commit/699fc72e Signed-off-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-07ACPICA: Add defines for the CXL Host Bridge Structure (CHBS)Alison Schofield1-0/+10
ACPICA commit 5ace82441a34f8d45725f12f6bd2677e79c186a6 CXL 2.0 defines length and version field values for the CHBS. Include them in the ACPI CEDT table definition. Link: https://github.com/acpica/acpica/commit/5ace8244 Signed-off-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: iASL: Add support for CEDT tableBob Moore1-1/+2
Also, update the CEDT template. ACPICA commit 1e6dded267b13c4aa0c3e16de0fa89d3b9c880e9 Link: https://github.com/acpica/acpica/commit/1e6dded2 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: CXL 2.0: CEDT: Add new CEDT tableBen Widawsky1-0/+43
ACPICA commit 0b03aa8ebd7a5b2b9407893f123ee587af45926f This sets up all of the boilerplate without actually doing anything. Link: https://github.com/acpica/acpica/commit/0b03aa8e Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07ACPICA: ACPI 6.4: HMAT: add new fields/flagsBob Moore1-3/+7
ACPICA commit 18a77ca6fc3edd26a24d8f32ae5c0ea66d84ccff Link: https://github.com/acpica/acpica/commit/18a77ca6 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-02-22Merge tag 'iommu-updates-v5.12' of ↵Linus Torvalds1-1/+10
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - ARM SMMU and Mediatek updates from Will Deacon: - Support for MT8192 IOMMU from Mediatek - Arm v7s io-pgtable extensions for MT8192 - Removal of TLBI_ON_MAP quirk - New Qualcomm compatible strings - Allow SVA without hardware broadcast TLB maintenance on SMMUv3 - Virtualization Host Extension support for SMMUv3 (SVA) - Allow SMMUv3 PMU perf driver to be built independently from IOMMU - Some tidy-up in IOVA and core code - Conversion of the AMD IOMMU code to use the generic IO-page-table framework - Intel VT-d updates from Lu Baolu: - Audit capability consistency among different IOMMUs - Add SATC reporting structure support - Add iotlb_sync_map callback support - SDHI support for Renesas IOMMU driver - Misc cleanups and other small improvments * tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits) iommu/amd: Fix performance counter initialization MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER iommu/mediatek: Fix error code in probe() iommu/mediatek: Fix unsigned domid comparison with less than zero iommu/vt-d: Parse SATC reporting structure iommu/vt-d: Add new enum value and structure for SATC iommu/vt-d: Add iotlb_sync_map callback iommu/vt-d: Move capability check code to cap_audit files iommu/vt-d: Audit IOMMU Capabilities and add helper functions iommu/vt-d: Fix 'physical' typos iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration] driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3 MAINTAINERS: Add entry for MediaTek IOMMU iommu/mediatek: Add mt8192 support iommu/mediatek: Remove unnecessary check in attach_device iommu/mediatek: Support master use iova over 32bit iommu/mediatek: Add iova reserved function iommu/mediatek: Support for multi domains iommu/mediatek: Add get_domain_id from dev->dma_range_map ...
2021-02-04iommu/vt-d: Add new enum value and structure for SATCYian Chen1-1/+10
Starting from Intel Platform VT-d v3.2, BIOS may provide new remapping structure SATC for SOC integrated devices, according to section 8.8 of Intel VT-d architecture specification v3.2. The SATC structure reports a list of the devices that require ATS for normal device operation. It is a functional requirement that these devices will not work without OS enabling ATS capability. This patch introduces the new enum value and structure to represent the remapping information. Kernel should parse the information from the reporting structure and enable ATC for the devices as needed. Signed-off-by: Yian Chen <yian.chen@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20210203093329.1617808-1-baolu.lu@linux.intel.com Link: https://lore.kernel.org/r/20210204014401.2846425-6-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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