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2026-06-09Merge tag 'renesas-pinctrl-for-v7.2-tag3' of ↵Linus Walleij1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v7.2 (take three) - Fix locking on RZ/G3L. * tag 'renesas-pinctrl-for-v7.2-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: pinctrl: renesas: rzg2l: Use raw_spinlock_irqsave() on power source update Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-06-05pinctrl: renesas: rzg2l: Use raw_spinlock_irqsave() on power source updateClaudiu Beznea1-1/+1
The rest of the driver uses raw_spin_lock_irqsave() and raw_spin_unlock_irqrestore() for locking. To avoid concurrency issues or deadlocks, use raw_spinlock_irqsave() via the scoped_guard() helper for power source updates as well. Fixes: bbe2277dedbe ("pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO}") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260603151642.4075678-2-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-01Merge tag 'renesas-pinctrl-for-v7.2-tag2' of ↵Linus Walleij3-14/+18
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v7.2 (take two) - Add GPIO config support on RZ/G2L, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-29pinctrl: Use named initializers for platform_device_id arraysUwe Kleine-König (The Capable Hub)1-12/+12
Named initializers are better readable and more robust to changes of the struct definition. This robustness is relevant for a planned change to struct platform_device_id replacing .driver_data by an anonymous unit. While touching these arrays unify spacing and usage of commas. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-05-28pinctrl: renesas: rzg2l: Use tab instead of spacesClaudiu Beznea1-1/+1
Use tab instead of spaces to follow the same coding style. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260528080439.615958-5-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-28pinctrl: renesas: rzg2l: Keep member documentation alignedClaudiu Beznea1-2/+2
Keep the documentation for struct rzg2l_pinctrl_reg_cache members aligned with the struct member order. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260528080439.615958-4-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-28pinctrl: renesas: rzv2m: Use -ENOTSUPP instead of -EOPNOTSUPPClaudiu Beznea1-2/+2
The pinctrl and GPIO core code make exceptions for the -ENOTSUPP error code. One such example is gpio_set_config_with_argument_optional(), which returns success when gpio_set_config_with_argument() returns -ENOTSUPP, but reports failure for all other error codes. Returning -EOPNOTSUPP from the pinctrl driver on the unsupported pinctrl operation may lead to boot failures when pinctrl drivers implements struct gpio_chip::set_config, the system uses GPIO hogs, and the struct gpio_chip::set_config implementation returns -EOPNOTSUPP for the unsupported operations. Currently, the driver does not implement struct gpio_chip::set_config(). To avoid future failures, return -ENOTSUPP from rzv2m_pinctrl_pinconf_set(). rzv2m_pinctrl_pinconf_group_get() is used when dumping pinctrl configuration. pinconf_generic_dump_one(), which calls it, makes exceptions for the -EINVAL and -ENOTSUPP error codes. The documentation for struct pinconf_ops::pin_config_group_get states that it "should return -ENOTSUPP and -EINVAL using the same rules as pin_config_get()". The documentation for struct pinconf_ops::pin_config_get states: "get the config of a certain pin, if the requested config is not available on this controller this should return -ENOTSUPP and if it is available but disabled it should return -EINVAL". Return -ENOTSUPP for the unsupported pinctrl operation. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260522105717.1727837-1-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25pinctrl: renesas: rzg2l: Populate struct gpio_chip::set_configClaudiu Beznea1-0/+1
Populate struct gpio_chip::set_config to allow various GPIO settings. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260515124008.2947838-3-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25pinctrl: renesas: rzg2l: Use -ENOTSUPP instead of -EOPNOTSUPPClaudiu Beznea1-4/+4
The pinctrl and GPIO core code make exceptions for the -ENOTSUPP error code. One such example is gpio_set_config_with_argument_optional(), which returns success when gpio_set_config_with_argument() returns -ENOTSUPP, but reports failure for all other error codes. Returning -EOPNOTSUPP from the pinctrl driver on the unsupported pinctrl operation may lead to boot failures when pinctrl drivers implements struct gpio_chip::set_config, the system uses GPIO hogs, and the struct gpio_chip::set_config implementation returns -EOPNOTSUPP for the unsupported operations. Return -ENOTSUPP for the unsupported pinctrl operation. Fixes: 560c633d378a ("pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks") Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260515124008.2947838-2-claudiu.beznea@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25pinctrl: renesas: rzt2h: Skip PFC mode configuration if already setLad Prabhakar1-1/+6
In rzt2h_pinctrl_set_pfc_mode(), read the PMC and PFC registers upfront and skip the pin function configuration if the pin is already in peripheral mode with the desired function. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260513115312.1574367-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25pinctrl: renesas: rzt2h: Remove unused variable in rzt2h_pinctrl_register()Lad Prabhakar1-4/+2
Variable 'j' in rzt2h_pinctrl_register() is incremented during pin descriptor initialization but never used afterwards. Remove the unused variable and the associated dead code. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260513115312.1574367-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-15pinctrl: renesas: sh-pfc: Implement .pin_config_group_get() callbackGeert Uytterhoeven1-0/+25
When reading /sys/kernel/debug/pinctrl/*.pinctrl-sh-pfc/pinconf-groups while CONFIG_DEBUG_PINCTRL is enabled, the user is confronted with a seemlingly endless stream of identical messages on the console: sh-pfc e6060000.pinctrl: cannot get configuration for pin group, missing group config get function in driver Fix this by implementing the sh_pfc_pinconf_ops.pin_config_group_get() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/130ce567f23fd6eef8f5fa7273480a0e3ff2d1d9.1777562482.git.geert+renesas@glider.be
2026-05-11pinctrl: renesas: rzv2m: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven1-1/+2
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/4bcb78b40d685b0aab8c3150d379240ffb765b37.1777562725.git.geert+renesas@glider.be
2026-05-11pinctrl: renesas: rzg2l: Fix type in .pin_config_group_get() callbackGeert Uytterhoeven1-1/+2
On 64-bit platforms, "unsigned long" is 64-bit. Hence checking if all "unsigned long" configuration values are equal should be done using an "unsigned long" temporary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/6befae30f129daffd94f7a9507d874443e444a21.1777562725.git.geert+renesas@glider.be
2026-05-11pinctrl: renesas: rzg2l: Add support for clone channel controlBiju Das1-0/+181
The RZ/G3L SoC has some IP such as I2C ch{2,3},SCIF ch{3,4,5}, RSPI ch{1,2} and RSCI ch{1,2,3} need to control the clone channel for proper operation. As per the RZ/G3L hardware manual, the clone channel setting is to be done before the mux setting. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()Biju Das1-4/+6
The port and function selectors are evaluated multiple times in rzg2l_pinctrl_set_mux(). Simplify the function by dropping dupicate evaluation storing them in local variables. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Add support for RZ/G3L SoCBiju Das1-0/+228
Add pinctrl driver support for RZ/G3L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Update OEN pin validation to use exact matchBiju Das1-1/+1
The RZ/G2L SoC uses pin 0 from a port for OEN while RZ/G3L uses pin 1. The existing greater-than comparison against oen_max_pin in rzg2l_pin_to_oen_bit() would incorrectly accept any pin below that value rather than enforcing the single valid OEN pin for each SoC. Replace the range check with an exact equality test so that only the designated OEN pin is accepted. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Add support for selecting power source for ↵Biju Das1-9/+44
{WDT,AWO,ISO} The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO by extending rzg2l_caps_to_pwr_reg() with a mask output parameter so that callers callers can identify which bit(s) within OTHER_POC correspond to the requested domain. Update rzg2l_get_power_source() to extract the relevant bit field via field_get() when reading OTHER_POC, and update rzg2l_set_power_source() to perform a read-modify-write under the spinlock when writing to OTHER_POC, since multiple domains share the same register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-11pinctrl: renesas: rzg2l: Make QSPI register handling conditionalBiju Das1-3/+8
The QSPI register at offset 0x3008 is not present on all SoCs supported by the RZ/G2L pinctrl driver. Unconditionally reading and writing this register during suspend/resume on hardware that lacks it can cause undefined behaviour. Add a qspi field to rzg2l_register_offsets to allow per-SoC declaration of the QSPI register offset, and guard the suspend/resume accesses with a check on that field. Populate the offset only for the RZ/{G2L,G2LC,G2UL, Five} hardware configuration, which is where the register is known to exist. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260430093422.74812-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in PMLad Prabhakar1-1/+18
On RZ/V2H(P), dedicated pins support pull-up/pull-down configuration via PIN_CFG_PUPD. Add PUPD handling for dedicated pins in the PM save/restore path. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resumeLad Prabhakar1-2/+35
Include the NOD (N-ch Open Drain) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM cacheLad Prabhakar1-1/+2
Include PIN_CFG_IOLH_RZV2H in the IOLH capability checks when saving and restoring pin configuration registers. On RZ/V2H(P), RZ/V2N, and RZ/G3E, the IOLH configuration is defined by the PIN_CFG_IOLH_RZV2H capability. The previous implementation did not account for this, causing the IOLH registers to be skipped during PM save/restore. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resumeLad Prabhakar1-3/+35
Include the SR (Slew Rate) register in the PM suspend/resume register cache. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Fix SMT register cache handlingLad Prabhakar1-7/+14
Store SMT register cache per bank instead of using a single array. On RZ/V2H(P), RZ/V2N, and RZ/G3E, the SMT register is split across two 32-bit registers: bits 0/8/16/24 control pins 0-3, while pins 4-7 are controlled by the corresponding bits in the next register. The previous implementation cached only a single SMT register, leading to incomplete save/restore of SMT state. Convert cache->smt to a per-bank array and allocate storage for both halves. Update suspend/resume handling to save and restore both SMT registers when present. Fixes: 837afa592c623 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins ↵Biju Das1-1/+1
during suspend/resume When saving/restoring pull-up/down register state during suspend/resume, the second PUPD register access was incorrectly using the same base offset as the first, effectively reading/writing the same register twice instead of the adjacent one. Add the correct + 4 byte offset to the second RZG2L_PCTRL_REG_ACCESS32 call so that pupd[1][port] is properly saved and restored from the next 32-bit register in the PUPD register pair, covering pins 4–7 of ports with 4 or more pins. Fixes: b2bd65fbb617 ("pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260328090548.84124-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-26pinctrl: renesas: rzg2l: Drop superfluous blank lineGeert Uytterhoeven1-1/+0
No need for a blank line after a "case" statement. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/7bfa105cf72d3b3e72a45d6218b5d88c8a7f520f.1774548955.git.geert+renesas@glider.be
2026-03-26pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registersBiju Das1-0/+7
The rzg2l_pinctrl_pm_setup_regs() handles save/restore of {IOLH,IEN,PUPD,SMT} registers during s2ram, but only for ports where all pins share the same pincfg. Extend the code to also support ports with variable pincfg per pin, so that {IOLH,IEN,PUPD,SMT} registers are correctly saved and restored for all pins. Fixes: 254203f9a94c ("pinctrl: renesas: rzg2l: Add suspend/resume support") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260326162459.101414-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-26pinctrl: renesas: rzt2h: Add pin configuration supportLad Prabhakar1-0/+258
Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control bias configuration, Schmitt trigger input, output slew rate, and drive strength. Implement pinconf_ops to allow reading and updating these properties through the generic pin configuration framework. The implementation supports bias-disable, bias-pull-up, bias-pull-down, input-schmitt-enable, slew-rate, and drive-strength-microamp. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-10pinctrl: renesas: rza1: Normalize return value of gpio_get()Dmitry Torokhov1-1/+1
The GPIO .get() callback is expected to return 0 or 1 (or a negative error code). Ensure that the value returned by rza1_gpio_get() is normalized to the [0, 1] range. Fixes: 86ef402d805d606a ("gpiolib: sanitize the return value of gpio_chip::get()") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/aZYnyl-Nf4S1U2yj@google.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06pinctrl: renesas: rzt2h: Fix invalid wait contextCosmin Tanislav1-7/+7
The rzt2h_gpio_get_direction() function is called from gpiod_get_direction(), which ends up being used within the __setup_irq() call stack when requesting an interrupt. __setup_irq() holds a raw_spinlock_t with IRQs disabled, which creates an atomic context. spinlock_t cannot be used within atomic context when PREEMPT_RT is enabled, since it may become a sleeping lock. An "[ BUG: Invalid wait context ]" splat is observed when running with CONFIG_PROVE_LOCKING enabled, describing exactly the aforementioned call stack. __setup_irq() needs to hold a raw_spinlock_t with IRQs disabled to serialize access against a concurrent hard interrupt. Switch to raw_spinlock_t to fix this. Fixes: 829dde3369a9 ("pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts") Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260205103930.666051-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-06pinctrl: renesas: rzt2h: Fix device node leak in rzt2h_gpio_register()Felix Gu1-0/+1
When calling of_parse_phandle_with_fixed_args(), the caller is responsible for calling of_node_put() to release the device node reference. In rzt2h_gpio_register(), the driver fails to call of_node_put() to release the reference in of_args.np, which causes a memory leak. Add the missing of_node_put() call to fix the leak. Fixes: 34d4d093077a ("pinctrl: renesas: Add support for RZ/T2H") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260127-rzt2h-v1-1-86472e7421b8@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds3-3/+3
This was done entirely with mindless brute force, using git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' | xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/' to convert the new alloc_obj() users that had a simple GFP_KERNEL argument to just drop that argument. Note that due to the extreme simplicity of the scripting, any slightly more complex cases spread over multiple lines would not be triggered: they definitely exist, but this covers the vast bulk of the cases, and the resulting diff is also then easier to check automatically. For the same reason the 'flex' versions will be done as a separate conversion. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook3-4/+3
This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook <kees@kernel.org>
2026-01-13pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interruptsCosmin Tanislav2-0/+205
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have IRQ-capable pins handled by the ICU, which forwards them to the GIC. The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, and the mapping is not configurable. Add a GPIO IRQ chip to the pin controller that can be used to configure these pins as IRQ lines. The pin controller places the requested pins into IRQ function, disabling GPIO mode. A hierarchical IRQ domain is used to forward other functionality to the parent IRQ domain, the ICU. The ICU does level translation and then forwards other functionality to the GIC. Wakeup capability is implemented by placing the entire pin controller on the wakeup path if any pins are requested to be wakeup-capable. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260109143910.645628-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09pinctrl: renesas: rzt2h: Allow .get_direction() for IRQ function GPIOsCosmin Tanislav1-1/+20
Setting up an IRQ would normally be done in the .activate() and .deactivate() ops of the IRQ domain, but for hierarchical IRQ domains the .activate() and .deactivate() ops are overridden in the gpiochip_hierarchy_setup_domain_ops() function. As such, activating and deactivating need to be done in the .translate() and .free() ops of the IRQ domain. For RZ/T2H and RZ/N2H, interrupts go through the pin controller, into the ICU, which level-translates them and forwards them to the GIC. To use a GPIO as an interrupt it needs to be put into peripheral function mode 0, which will connect it to the IRQ lines of the ICU. The IRQ chip .child_to_parent_hwirq() callback is called as part of the IRQ fwspec parsing logic (as part of irq_create_of_mapping()) which happens before the IRQ is requested (as part of gpiochip_lock_as_irq()). gpiochip_lock_as_irq() calls gpiod_get_direction() if the .get_direction() callback is provided to ensure that the GPIO line is set up as input. In our case, IRQ function is separate from GPIO, and both cannot be true at the same time. Return GPIO_LINE_DIRECTION_IN even if pin is in IRQ function to allow this setup to work. Hold the spinlock to ensure atomicity between reading the PMC register (which determines whether the pin is in GPIO mode or not) and reading the function of the pin when it is not in GPIO mode. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09pinctrl: renesas: rzt2h: Move GPIO enable/disable into separate functionCosmin Tanislav1-8/+16
GPIO is enabled or disabled in multiple places, simplify code by moving this logic into a separate function. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-13pinctrl: renesas: rzg2l: Refactor OEN register PWPR handlingJohn Madieu1-20/+33
Extract the OEN register write with PWPR protection logic into a helper function to eliminate code duplication between rzg2l_write_oen() and rzg2l_pinctrl_resume_noirq(). Introduce rzg2l_oen_write_with_pwpr() helper that encapsulates the PWPR unlock, OEN register write, and PWPR lock sequence. This helper must be called with pctrl->lock already held by the caller. Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/cip-dev/OS9PR01MB16368C765305362F5F4132759FFC4A@OS9PR01MB16368.jpnprd01.prod.outlook.com/T/#u Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251106080758.36645-1-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-10pinctrl: renesas: r8a779h0: Remove STPWT_EXTFXRGeert Uytterhoeven1-2/+1
Rev.0.81 of the R-Car V4M Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/f849fa3b9b516e9dd04b45462b69f52225259480.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779h0: Remove CC5_OSCOUTHuy Bui1-2/+1
Rev.0.71 of the R-Car V4M Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/895bb560467309706931d14aeea0e063ad0e86eb.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove STPWT_EXTFXRHuy Bui1-2/+1
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/f6cfdbbc024d85e87583a1d57ea01582632f1216.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove CC5_OSCOUTHuy Bui1-2/+1
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/77f9efe5388f2801ace945b7793d4823618eeec8.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove AVB[01]_MIIThanh Quan1-64/+32
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "AVB[01]_MII_*" signals from the pin control register tables. As these are further unused in the pin control driver, they can be removed safely. Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/58662f50136280532bcc8bbe94741d82425bd118.1762274384.git.geert+renesas@glider.be
2025-10-27pinctrl: renesas: rzg2l: Remove useless wrappersCosmin Tanislav1-13/+3
rzg2l_gpio_irq_set_type() and rzg2l_gpio_irqc_eoi() only call the equivalent parent functions, replace their usage with the parent functions and remove them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251022074100.1994447-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-23pinctrl: renesas: rza1: Make mux_conf const in rza1_pin_mux_single()Geert Uytterhoeven1-3/+3
The rza1_mux_conf object pointed to by the mux_conf parameter of rza1_pin_mux_single() is never modified. Make it const. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://patch.msgid.link/168e06bc57081aa3c42ff9aa2740a0a108df7d34.1761033950.git.geert+renesas@glider.be
2025-10-14pinctrl: renesas: Remove unneeded semicolonsGeert Uytterhoeven2-7/+7
Semicolons after end of function braces are not needed, remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/99db8c1bfb64980b54a4b5c4988c7935609133e1.1758718027.git.geert+renesas@glider.be
2025-10-14pinctrl: renesas: rzg2l: Remove extra semicolonsCosmin Tanislav1-5/+5
Semicolons after end of function braces are unnecessary, remove them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250923174951.1136259-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-14pinctrl: renesas: rzg2l: Fix PMC restoreBiju Das1-1/+5
PMC restore needs unlocking the register using the PWPR register. Fixes: ede014cd1ea6422d ("pinctrl: renesas: rzg2l: Add function pointer for PMC register write") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250921111557.103069-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-14pinctrl: renesas: Drop duplicate newlinesMarek Vasut15-17/+0
Remove duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250918200409.37284-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-14pinctrl: renesas: rzg2l: Drop unnecessary pin configurationsBiju Das1-6/+19
There is no need to reconfigure a pin if the pin's configuration values are the same as the reset values. E.g. the PS0 pin configuration for the NMI function is PMC = 1 and PFC = 0, which is the same as the reset values. Currently the code is first setting it to GPIO HI-Z state and then again reconfiguring to the NMI function, leading to spurious IRQs. Fix this by dropping unnecessary pin configuration from the driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250909104247.3309-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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