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path: root/drivers/media/i2c/ccs-pll.c
AgeCommit message (Expand)AuthorFilesLines
2026-03-11media: ccs-pll: Fix pre-PLL divider calculation for EXT_IP_PLL_DIVIDER flagAlexander Shiyan1-3/+2
2025-05-06media: ccs-pll: Print a debug message when VT tree calculation failsLaurent Pinchart1-2/+2
2025-04-25media: ccs-pll: Document the CCS PLL flagsSakari Ailus1-1/+1
2025-04-25media: ccs-pll: Print PLL calculator flags in the beginningSakari Ailus1-1/+6
2025-04-25media: ccs-pll: Better validate VT PLL branchSakari Ailus1-3/+9
2025-04-25media: ccs-pll: Add a flag for even PLL multipliersSakari Ailus1-1/+10
2025-04-25media: ccs-pll: Print missing PLL flagsSakari Ailus1-1/+3
2025-04-25media: ccs-pll: Drop LINK_DECOUPLED flagSakari Ailus1-2/+1
2025-04-25media: ccs-pll: Print a debug message on too high VT PLL OP clockSakari Ailus1-4/+5
2025-04-25media: ccs-pll: Correct the upper limit of maximum op_pre_pll_clk_divSakari Ailus1-1/+1
2025-04-25media: ccs-pll: Check for too high VT PLL multiplier in dual PLL caseSakari Ailus1-0/+5
2025-04-25media: ccs-pll: Start VT pre-PLL multiplier search from correct valueSakari Ailus1-0/+2
2025-04-25media: ccs-pll: Start OP pre-PLL multiplier search from correct valueSakari Ailus1-0/+2
2025-03-06media: ccs-pll: Make variables const where appropriateLaurent Pinchart1-8/+8
2023-08-10media: ccs-pll: Initialise best_div to avoid a compiler warningSakari Ailus1-1/+1
2021-02-01Merge tag 'v5.11-rc6' into patchworkMauro Carvalho Chehab1-7/+1
2021-01-12media: Revert "media: ccs-pll: Fix MODULE_LICENSE"Sakari Ailus1-1/+1
2021-01-12media: ccs-pll: Switch from standard integer types to kernel onesSakari Ailus1-57/+57
2021-01-07media: ccs-pll: Fix link frequency for C-PHYSakari Ailus1-7/+1
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus1-0/+5
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus1-20/+44
2020-12-07media: ccs: Dual PLL supportSakari Ailus1-2/+7
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus1-22/+195
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus1-27/+37
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus1-5/+7
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus1-26/+25
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus1-57/+91
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus1-19/+66
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus1-23/+31
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus1-29/+55
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus1-124/+131
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus1-9/+26
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus1-0/+9
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus1-7/+19
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus1-6/+13
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus1-1/+3
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus1-15/+7
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus1-11/+25
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus1-2/+2
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus1-2/+1
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus1-2/+9
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus1-8/+4
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus1-1/+1
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus1-5/+0
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus1-2/+8
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus1-2/+2
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus1-136/+146
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus1-1/+1
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