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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola1-0/+1
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola1-0/+13
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola3-3/+37
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola1-0/+10
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola4-40/+45
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola1-0/+1
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola2-2/+3
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola1-0/+1
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola2-0/+58
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola1-0/+69
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko1-2/+2
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko1-4/+2
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola3-35/+40
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola1-0/+19
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola3-117/+0
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak1-3/+15
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak1-1/+3
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak1-12/+5
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak1-7/+36
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak1-0/+25
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak1-2/+8
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak2-7/+49
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak1-1/+6
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak1-105/+98
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak2-32/+92
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak1-21/+47
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak1-9/+14
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak1-27/+35
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola1-15/+15
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko2-4/+2
2025-11-19drm/amdgpu: Switch to use %ptSpAndy Shevchenko1-2/+1
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian1-4/+7
2025-11-18drm/xe/vf: Shadow buffer management for CCS read/write operationsSatyanarayana K V P4-7/+73
2025-11-18drm/xe/sa: Shadow buffer support in the sub-allocator poolSatyanarayana K V P5-4/+91
2025-11-18drm/xe/irq: Handle msix vector0 interruptVenkata Ramana Nayana1-17/+1
2025-11-18drm/xe: Remove duplicate DRM_EXEC selection from KconfigShuicheng Lin1-1/+0
2025-11-18drm/xe/kunit: Fix forcewake assertion in mocs testMatt Roper1-1/+1
2025-11-18drm/xe: Prevent BIT() overflow when handling invalid prefetch regionShuicheng Lin1-2/+4
2025-11-18drm/radeon: delete radeon_fence_process in is_signaled, no deadlockRobert McClinton1-7/+0
2025-11-18drm/amd/display: Fix pbn to kbps ConversionFangzhi Zuo1-36/+23
2025-11-18drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5Ivan Lipski1-0/+8
2025-11-18drm/amd/display: Add an HPD filter for HDMIIvan Lipski2-0/+144
2025-11-18drm/amd/display: Increase DPCD read retriesMario Limonciello (AMD)1-1/+1
2025-11-18drm/msm/a8xx: Add support for Adreno X2-85 GPUAkhil P Oommen3-0/+140
2025-11-18drm/msm/adreno: Do CX GBIF config before GMU startAkhil P Oommen5-14/+54
2025-11-18drm/msm/a8xx: Add support for Adreno 840 GPUAkhil P Oommen5-1/+174
2025-11-18drm/msm/adreno: Support AQE engineAkhil P Oommen4-0/+28
2025-11-18drm/msm/adreno: Introduce A8x GPU SupportAkhil P Oommen7-34/+1321
2025-11-18drm/msm/a6xx: Share dependency vote table with GMUAkhil P Oommen4-0/+125
2025-11-18drm/msm/a6xx: Improve MX rail fallback in RPMH vote initAkhil P Oommen1-11/+15
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