aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2025-10-28drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on FijiJohn Smith1-1/+1
2025-10-28drm/amd/pm: fix smu table id bound check issue in smu_cmn_update_table()Yang Wang1-1/+1
2025-10-28drm/amd/display: Don't program BLNDGAM_MEM_PWR_FORCE when CM low-power is dis...Matthew Schwartz1-3/+0
2025-10-28drm/amdgpu: Add uniras version in sysfsJinzhou Su1-1/+31
2025-10-28drm/amdgpu: get rev_id from strap register or IP-discovery tablePerry Yuan2-11/+17
2025-10-28drm/amdgpu: clear bad page info of ras moduleJinzhou Su1-0/+22
2025-10-28drm/amd/display: pause the workload setting in dmKenneth Feng1-0/+11
2025-10-28drm/radeon: Remove calls to drm_put_dev()Daniel Palmer1-21/+4
2025-10-28drm/radeon: Do not kfree() devres managed rdevDaniel Palmer1-1/+0
2025-10-28drm/radeon: Clean up pdev->dev instances in probeDaniel Palmer1-4/+5
2025-10-28drm/amd: Check that VPE has reached DPM0 in idle handlerMario Limonciello1-4/+30
2025-10-28drm/sched: avoid killing parent entity on child SIGKILLDavid Rosca1-1/+2
2025-10-28drm/ttm: add pgprot handling for RISC-VIcenowy Zheng1-1/+2
2025-10-27drm/etnaviv: fix flush sequence logicTomeu Vizoso1-1/+1
2025-10-27drm/xe/pf: Access VF's register using dedicated MMIO viewMichal Wajdeczko3-28/+41
2025-10-27drm/xe/xe3: Add WA_14024681466 for Xe3_LPGNitin Gote2-0/+5
2025-10-27drm/xe/pf: Fix VF FLR synchronization between all GTsMichal Wajdeczko1-0/+2
2025-10-27drm/xe: Fix spelling and typos across Xe driver filesSanjay Yadav32-63/+63
2025-10-27drm/nouveau: Fix race in nouveau_sched_fini()Philipp Stanner1-2/+12
2025-10-27drm/sched: Fix race in drm_sched_entity_select_rq()Philipp Stanner1-1/+2
2025-10-27Merge 6.18-rc3 into driver-core-nextGreg Kroah-Hartman61-287/+468
2025-10-26drm/gem-atomic: Reset plane state to NULL if allocation failedThomas Zimmermann1-2/+0
2025-10-26drm/sysfb: Do not dereference NULL pointer in plane resetThomas Zimmermann1-2/+6
2025-10-25drm/msm: Ensure vm is created in VM_BIND ioctlRob Clark1-1/+1
2025-10-25drm/msm: Reject MAP_NULL op if no PRRRob Clark3-7/+17
2025-10-24drm/xe/configfs: Drop MAX_GT_TYPE_CHARS constantMatt Roper1-2/+1
2025-10-25drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()Ville Syrjälä1-2/+4
2025-10-25drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() commentVille Syrjälä1-4/+2
2025-10-25drm/i915/vrr: Nuke intel_vrr_vmin_flipline()Ville Syrjälä1-7/+2
2025-10-25drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()Ville Syrjälä1-6/+2
2025-10-25drm/i915/vrr: s/crtc_state/old_crtc_state/ in intel_vrr_transcoder_disable()Ville Syrjälä1-4/+4
2025-10-25drm/i915/vrr: Move HAS_VRR() check into intel_vrr_set_transcoder_timings()Ville Syrjälä2-2/+4
2025-10-25drm/i915/vrr: Remove redundant HAS_VRR() checksVille Syrjälä1-6/+0
2025-10-25drm/i915/vrr: Always write TRANS_VRR_CTL in intel_vrr_set_transcoder_timings(...Ville Syrjälä1-9/+3
2025-10-25drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on always...Ville Syrjälä1-1/+2
2025-10-25drm/i915/vrr: Extract intel_vrr_tg_enable()Ville Syrjälä1-19/+25
2025-10-25drm/i915/vrr: Extract intel_vrr_tg_disable()Ville Syrjälä1-23/+19
2025-10-25drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()Ville Syrjälä1-1/+2
2025-10-25drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings()Ville Syrjälä1-23/+12
2025-10-25drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()Ville Syrjälä1-3/+3
2025-10-25drm/i915/vrr: Extract intel_vrr_set_vrr_timings()Ville Syrjälä1-4/+12
2025-10-25drm/i915/vrr: Move compute_fixed_rr_timings()Ville Syrjälä1-9/+9
2025-10-25drm/i195/vrr: Move crtc_state->vrr.{vmin,vmax} update into intel_vrr_compute_...Ville Syrjälä1-7/+7
2025-10-25drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bitVille Syrjälä1-1/+2
2025-10-25drm/i915/vrr: Compute fixed refresh rate timings the same way as CMRR timingsVille Syrjälä1-5/+3
2025-10-24drm/i915: Remove the "vblank delay" state dumpVille Syrjälä1-3/+1
2025-10-24drm/i915/lrr: Include SCL in lrr_params_changed()Ville Syrjälä1-5/+8
2025-10-24drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGLVille Syrjälä1-0/+6
2025-10-24drm/gud: rearrange gud_probe() to prepare for function splittingRuben Wauters1-21/+24
2025-10-24Merge drm/drm-next into drm-misc-nextThomas Zimmermann184-2295/+4979
generated by cgit