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2026-04-28clk: rk808: fix OF node reference imbalanceJohan Hovold1-1/+1
The driver reuses the OF node of the parent multi-function device but fails to take another reference to balance the one dropped by the platform bus code when unbinding the MFD and deregistering the child devices. Fix this by using the intended helper for reusing OF nodes. Fixes: 2dc51ca822e4 ("clk: RK808: Reduce 'struct rk808' usage") Cc: stable@vger.kernel.org # 6.5 Cc: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-28clk: eyeq: add EyeQ5 children auxiliary device for generic PHYsThéo Lebrun1-0/+3
Grow our clk-eyeq family; it knows how to spawn reset provider and pin controller children. Expand with a generic PHY driver on EyeQ5. Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-28clk: eyeq: use the auxiliary device creation helperJerome Brunet1-45/+12
The auxiliary device creation of this driver is simple enough to use the available auxiliary device creation helper. Use it and remove some boilerplate code. Tested-by: Théo Lebrun <theo.lebrun@bootlin.com> # On Mobileye EyeQ5 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-28clk: spacemit: k3: mark top_dclk as CLK_IS_CRITICALTroy Mitchell1-1/+1
top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, all memory-mapped bus transactions cease to function, causing DMA engines to hang and general system instability. Mark it CLK_IS_CRITICAL so the CCF never gates it during the unused clock sweep. Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-26Merge tag 'clk-for-linus' of ↵Linus Torvalds1-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "One more fix for the merge window to avoid a boot hang on Raspberry Pi 3B by marking the VEC clk critical so that it doesn't get turned off and hang the bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED
2026-04-25clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSEDMaíra Canal1-0/+7
On Raspberry Pi 3B, the VEC clock is used by the VideoCore firmware display driver, which remains active until the vc4 driver loads and sends NOTIFY_DISPLAY_DONE. If this clock is disabled during boot, a bus lockup happens and the firmware becomes unresponsive, causing a complete system lockup. Mark the VEC clock with CLK_IGNORE_UNUSED so it survives the unused clock disablement and remains available until the vc4 driver takes over display management. Fixes: 672299736af6 ("clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks") Reported-by: Mark Brown <broonie@kernel.org> Closes: https://lore.kernel.org/r/5f0bec08-f458-4fba-8bf3-06817a100c4c@sirena.org.uk Signed-off-by: Maíra Canal <mcanal@igalia.com> Link: https://patch.msgid.link/20260401111416.562279-2-mcanal@igalia.com Tested-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Brian Masney <bmasney@redhat.com> # Active contributor to clk Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-21Merge tag 'clk-for-linus' of ↵Linus Torvalds129-3028/+22878
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We've finally gotten rid of the struct clk_ops::round_rate() code after months of effort from Brian Masney. Now the only option is to use determine_rate(), which is good because that takes a struct argument instead of just a couple unsigned longs, allowing us to easily modify the way we determine and set rates in the clk tree. Beyond that core framework change we've got the typical pile of new SoC clk driver additions, fixes for clk data and/or adding missing clks because the consumer driver using those clks wasn't ready, etc. The usual suspects are all here: Qualcomm, Samsung, Mediatek, and Rockchip along with some newcomers making RISC-V SoCs like ESWIN's eic700 and Tenstorrent's Atlantis. The clk driver side of this looks pretty normal. Core: - Remove the round_rate() clk op (yay!) New Drivers: - ESWIN eic700 SoC clk support - Econet EN751221 SoC clock/reset support - Global TCSR, RPMh, and display clock controller support for the Qualcomm Eliza platform - TCSR, the multiple global, and the RPMh clock controller support for the Qualcomm Nord platform - GPU clock controller support for Qualcomm SM8750 - Video and GPU clock controller support for Qualcomm Glymur - Global clock controller support for Qualcomm IPQ5210 - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock controllers on the SoC - ExynosAutov920: Add G3D (GPU) clock controller - Clock driver for the Rockchip RV1103B SoC - Initial support for the Renesas RZ/G3L (R9A08G046) SoC - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits) clk: visconti: pll: initialize clk_init_data to zero clk: fsl-sai: Add MCLK generation support clk: fsl-sai: Extract clock setup into fsl_sai_clk_register() dt-bindings: clock: fsl-sai: Document clock-cells = <1> support clk: fsl-sai: Add i.MX8M support with 8 byte register offset clk: fsl-sai: Sort the headers dt-bindings: clock: fsl-sai: Document i.MX8M support clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support ...
2026-04-17Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2-13/+81
Pull MIPS updates from Thomas Bogendoerfer: - Support for Mobileye EyeQ6Lplus - Cleanups and fixes * tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS/mtd: Handle READY GPIO in generic NAND platform data MIPS/input: Move RB532 button to GPIO descriptors MIPS: validate DT bootargs before appending them MIPS: Alchemy: Remove unused forward declaration MAINTAINERS: Mobileye: Add EyeQ6Lplus files MIPS: config: add eyeq6lplus_defconfig MIPS: Add Mobileye EyeQ6Lplus evaluation board dts MIPS: Add Mobileye EyeQ6Lplus SoC dtsi clk: eyeq: Add Mobileye EyeQ6Lplus OLB clk: eyeq: Adjust PLL accuracy computation clk: eyeq: Skip post-divisor when computing PLL frequency pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB pinctrl: eyeq5: Use match data reset: eyeq: Add Mobileye EyeQ6Lplus OLB MIPS: Add Mobileye EyeQ6Lplus support dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC MIPS: dts: loongson64g-package: Switch to Loongson UART driver mips: pci-mt7620: rework initialization procedure mips: pci-mt7620: add more register init values ...
2026-04-16Merge tag 'soc-drivers-7.1' of ↵Linus Torvalds2-3/+5
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
2026-04-16Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and ↵Stephen Boyd91-2919/+18268
'clk-cleanup' into clk-next * clk-samsung: clk: samsung: exynos850: Add APM-to-AP mailbox clock dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock clk: samsung: Use %pe format to simplify clk: samsung: pll: Fix possible truncation in a9fraco recalc rate clk: samsung: exynosautov920: add block G3D clock support dt-bindings: clock: exynosautov920: add G3D clock definitions clk: samsung: gs101: harmonise symbol names (clock arrays) clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC clk: samsung: Add clock PLL support for ARTPEC-9 SoC dt-bindings: clock: Add ARTPEC-9 clock controller * clk-qcom: (67 commits) clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains dt-bindings: clock: qcom: Add missing power-domains property clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock clk: qcom: dispcc-sc7180: Add missing MDSS resets ... * clk-round: clk: divider: remove divider_round_rate() and divider_round_rate_parent() clk: divider: remove divider_ro_round_rate_parent() clk: remove round_rate() clk ops clk: composite: convert from round_rate() to determine_rate() clk: test: remove references to clk_ops.round_rate * clk-sai: clk: fsl-sai: Add MCLK generation support clk: fsl-sai: Extract clock setup into fsl_sai_clk_register() dt-bindings: clock: fsl-sai: Document clock-cells = <1> support clk: fsl-sai: Add i.MX8M support with 8 byte register offset clk: fsl-sai: Sort the headers dt-bindings: clock: fsl-sai: Document i.MX8M support * clk-cleanup: clk: visconti: pll: initialize clk_init_data to zero clk: xgene: Fix mapping leak in xgene_pllclk_init() clk: Simplify clk_is_match() clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init clk: qoriq: avoid format string warning
2026-04-16Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and ↵Stephen Boyd17-8/+1658
'clk-allwinner' into clk-next * clk-tenstorrent: clk: tenstorrent: Add Atlantis clock controller driver reset: tenstorrent: Add reset controller for Atlantis dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu * clk-rockchip: clk: rockchip: rk3568: Add PCIe pipe clock gates clk: rockchip: Add clock controller for the RV1103B dt-bindings: clock: rockchip: Add RV1103B CRU support * clk-imx: clk: imx8mq: Correct the CSI PHY sels clk: vf610: Add support for the Ethernet switch clocks dt-bindings: clock: vf610: Add definitions for MTIP L2 switch dt-bindings: clock: vf610: Drop VF610_CLK_END define clk: vf610: Move VF610_CLK_END define to clk-vf610 driver clk: imx: imx8-acm: fix flags for acm clocks clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels() clk: imx: imx6q: Fix device node reference leak in pll6_bypassed() clk: imx: fracn-gppll: Add 477.4MHz support clk: imx: fracn-gppll: Add 333.333333 MHz support clk: imx: pll14xx: Use unsigned format specifier dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad * clk-allwinner: clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
2026-04-16Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and ↵Stephen Boyd22-98/+2945
'clk-mediatek' into clk-next - ESWIN eic700 SoC clk support - Econet EN751221 SoC clock/reset support * clk-fixes: clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc() clk: microchip: mpfs-ccc: fix out of bounds access during output registration clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source * clk-renesas: clk: renesas: Add support for RZ/G3L SoC dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC clk: renesas: rzg2l: Re-enable critical module clocks during resume clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper() clk: renesas: rzg2l: Add helper for mod clock enable/disable clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries clk: renesas: rzg2l: Add support for critical resets clk: renesas: r9a09g056: Remove entries for WDT{0,2,3} clk: renesas: r9a06g032: Enable watchdog reset sources clk: renesas: cpg-mssr: Use struct_size() helper clk: renesas: r9a09g047: Add PCIe clocks and reset clk: renesas: r9a09g057: Add PCIe clocks and reset clk: renesas: r9a09g056: Add PCIe clocks and reset clk: renesas: r9a09g047: Add entries for the RSPIs clk: renesas: r9a09g056: Add clock and reset entries for RTC clk: renesas: r9a09g057: Remove entries for WDT{0,2,3} clk: renesas: r9a09g056: Fix ordering of module clocks array clk: renesas: r9a09g057: Fix ordering of module clocks array * clk-rpi: clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks * clk-eswin: MAINTAINERS: Add entry for ESWIN EIC7700 clock driver clk: eswin: Add eic7700 clock driver clk: divider: Add devm_clk_hw_register_divider_parent_data dt-bindings: clock: eswin: Documentation for eic7700 SoC * clk-mediatek: clk: airoha: Add econet EN751221 clock/reset support to en7523-scu dt-bindings: clock, reset: Add econet EN751221
2026-04-13clk: eyeq: Add Mobileye EyeQ6Lplus OLBBenoît Monin2-2/+72
Declare the PLLs and fixed factors found in the EyeQ6Lplus OLB as part of the match data for the "mobileye,eyeq6lplus-olb" compatible. The PLL and fixed factor of the CPU are registered in early init as they are required during the boot by the GIC timer. Also select clk-eyeq for all EYEQ SoCs instead of listing each one individually, as it is needed by all Mobileye EyeQ SoC. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-13clk: eyeq: Adjust PLL accuracy computationBenoît Monin1-9/+9
The spread spectrum of the PLL found in eyeQ OLB is in 1/1024 parts of the frequency, not in 1/1000, so adjust the computation of the accuracy. Also correct the downspreading to match. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-13clk: eyeq: Skip post-divisor when computing PLL frequencyBenoît Monin1-2/+0
The output of the PLL is routed before the post-divisor so it should be ignored when computing the frequency of the PLL, functional change is implemented to reflect how the clock signal is wired internally. For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact as the post-divisor is either reported as disabled or set to 1. The PLL frequency is the same before and after the post-divisor. For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must be ignored to compute the correct frequency. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2026-04-11clk: visconti: pll: initialize clk_init_data to zeroBrian Masney1-1/+1
Sashiko reported the following: > The struct clk_init_data init is declared on the stack without being > fully zero-initialized. While fields like name, flags, parent_names, > num_parents, and ops are explicitly assigned, the parent_data and > parent_hws fields are left containing stack garbage. clk_core_populate_parent_map() currently prefers the parent names over the parent data and hws, so this isn't a problem at the moment. If that ordering ever changed in the future, then this could lead to some unexpected crashes. Let's just go ahead and make sure that the struct clk_init_data is initialized to zero as a good practice. Fixes: b4cbe606dc367 ("clk: visconti: Add support common clock driver and reset driver") Link: https://sashiko.dev/#/patchset/20260326042317.122536-1-rosenp%40gmail.com Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-11clk: fsl-sai: Add MCLK generation supportMarek Vasut1-1/+33
The driver currently supports generating BCLK. There are systems which require generation of MCLK instead. Register new MCLK clock and handle clock-cells = <1> to differentiate between BCLK and MCLK. In case of a legacy system with clock-cells = <0>, the driver behaves as before, i.e. always returns BCLK. Note that it is not possible re-use the current SAI audio driver to generate MCLK and correctly enable and disable the MCLK. If SAI (audio driver) is used to control the MCLK enablement, then MCLK clock is not always enabled, and it is not necessarily enabled when the codec may need the clock to be enabled. There is also no way for the codec node to specify phandle to clock provider in DT, because the SAI (audio driver) is not clock provider. If SAI (clock driver) is used to control the MCLK enablement, then MCLK clock is enabled when the codec needs the clock enabled, because the codec is the clock consumer and the SAI (clock driver) is the clock provider, and the codec driver can request the clock to be enabled when needed. There is also the usual phandle to clock provider in DT, because the SAI (clock driver) is clock provider. Acked-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Marek Vasut <marex@nabladev.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-11clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()Marek Vasut1-27/+63
Create helper function fsl_sai_clk_register() to set up and register SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_ prefix. Use of_node_full_name(dev->of_node) and clock name to register uniquely named clock. This is done in preparation for the follow up patch, which adds MCLK support. Signed-off-by: Marek Vasut <marex@nabladev.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-11clk: fsl-sai: Add i.MX8M support with 8 byte register offsetMarek Vasut2-5/+25
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Add support for the i.MX8M variant of the IP with this register shift and additional clock. Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-11clk: fsl-sai: Sort the headersMarek Vasut1-2/+2
Sort the headers. No functional change. Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-04-11Merge tag 'clk-remove-deprecated-apis-v7.1' of ↵Stephen Boyd4-110/+27
ssh://github.com/masneyb/linux into clk-round Pull round_rate refactoring from Brian Masney: Now that all of the dependencies across the tree have been merged into Linus's tree, here's a small series with the following changes: - Converts clk-composite from round_rate() to determine_rate() - Removes the round_rate() clk op - Removes the deprecated functions divider_round_rate(), divider_round_rate_parent(), and divider_ro_round_rate_parent() since these are just wrappers for the corresponding determine_rate variant * tag 'clk-remove-deprecated-apis-v7.1' of ssh://github.com/masneyb/linux: clk: divider: remove divider_round_rate() and divider_round_rate_parent() clk: divider: remove divider_ro_round_rate_parent() clk: remove round_rate() clk ops clk: composite: convert from round_rate() to determine_rate() clk: test: remove references to clk_ops.round_rate
2026-04-11Merge tag 'qcom-clk-for-7.1' of ↵Stephen Boyd62-176/+16593
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clock driver updates from Bjorn Andersson: - Global TCSR, RPMh, and display clock controller support for the Qualcomm Eliza platform - TCSR, the multiple global, and the RPMh clock controller support for the Qualcomm Nord platform - GPU clock controller support for Qualcomm SM8750 - Video and GPU clock controller support for Qualcomm Glymur - Global clock controller support for Qualcomm IPQ5210 - Introduce various smaller display-related fixes across Qualcomm Kaanapali, Milos, SC8280XP, SM4450, SM8250, and SA8775P. - Add missing GDSCs and fix retention flags for PCIe and USB power domains on SC8180X. - Enable runtime PM support to ensure performance votes are propagated to CX on Qualcomm platforms. - Mark the USB QTB clock as always-on on Qualcomm Hamoa, in order to ensure the SMMU can work even when USB controller device is sleeping. - Qualcomm IPQ6018 and IPQ8074 support in the IPQ CMN PLL driver - MDSS resets for Qualcomm SC7180, SM6115, and SM6125, to allow display subsystem driver to reset the hardware from the state left by the bootloader. * tag 'qcom-clk-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits) clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains dt-bindings: clock: qcom: Add missing power-domains property clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock clk: qcom: dispcc-sc7180: Add missing MDSS resets ...
2026-04-11Merge tag 'samsung-clk-7.1' of ↵Stephen Boyd8-37/+1505
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung Pull Samsung SoC clock driver updates from Krzysztof Kozlowski: - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock controllers on the SoC - ExynosAutov920: Add G3D (GPU) clock controller - Exynos850: Define missing clock for the APM mailbox * tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: exynos850: Add APM-to-AP mailbox clock dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock clk: samsung: Use %pe format to simplify clk: samsung: pll: Fix possible truncation in a9fraco recalc rate clk: samsung: exynosautov920: add block G3D clock support dt-bindings: clock: exynosautov920: add G3D clock definitions clk: samsung: gs101: harmonise symbol names (clock arrays) clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC clk: samsung: Add clock PLL support for ARTPEC-9 SoC dt-bindings: clock: Add ARTPEC-9 clock controller
2026-04-11Merge tag 'sunxi-clk-for-7.1' of ↵Stephen Boyd1-1/+16
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Chen-Yu Tsai: Just one change for this cycle, implementing support for the r-spi module clock in the A523 PRCM block, which was somehow missing during the initial bring-up. * tag 'sunxi-clk-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
2026-04-11Merge tag 'qcom-clk-fixes-for-7.0' of ↵Stephen Boyd1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull a Qualcomm clk driver fix from Bjorn Andersson - Fix the clock ops for SM8450 DPTX1 aux clock src to ensure DisplayPort works * tag 'qcom-clk-fixes-for-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source
2026-04-11Merge tag 'spacemit-clk-fixes-for-7.0-1' of ↵Stephen Boyd1-1/+1
ssh://github.com/spacemit-com/linux into clk-fixes Pull a SpacemiT clk fix from Yixun Lan: - Fix inverted condition check * tag 'spacemit-clk-fixes-for-7.0-1' of ssh://github.com/spacemit-com/linux: clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
2026-04-11Merge tag 'clk-microchip-fixes-7.0' of ↵Stephen Boyd1-1/+5
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-fixes Pull a microchip clk driver fix from Claudiu Beznea: - Fix out of bounds access for MPFS CCC clock controller * tag 'clk-microchip-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: microchip: mpfs-ccc: fix out of bounds access during output registration
2026-04-11Merge tag 'clk-imx-7.1' of ↵Stephen Boyd6-7/+32
git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clock driver updates from Abel Vesa: - Add optional ENET reference pad clock inputs for i.MX6Q/UL - Fix debug output in PLL14xx driver to use unsigned format specifier - Add 333.333 MHz and 477.4 MHz support to fracn-gppll for display use cases - Fix device node reference leaks in i.MX6 driver - Fix device node reference leak in of_assigned_ldb_sels() - Fix ACM clock flags on i.MX8 to prevent SAI sysclk failures - Move VF610_CLK_END define into the driver - Add VF610 Ethernet switch clock support - Correct CSI PHY parent clock selection on i.MX8MQ * tag 'clk-imx-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx8mq: Correct the CSI PHY sels clk: vf610: Add support for the Ethernet switch clocks dt-bindings: clock: vf610: Add definitions for MTIP L2 switch dt-bindings: clock: vf610: Drop VF610_CLK_END define clk: vf610: Move VF610_CLK_END define to clk-vf610 driver clk: imx: imx8-acm: fix flags for acm clocks clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels() clk: imx: imx6q: Fix device node reference leak in pll6_bypassed() clk: imx: fracn-gppll: Add 477.4MHz support clk: imx: fracn-gppll: Add 333.333333 MHz support clk: imx: pll14xx: Use unsigned format specifier dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad
2026-04-11Merge tag 'v7.1-rockchip-clk1' of ↵Stephen Boyd5-0/+721
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Clock driver for the Rockchip RV1103B SoC For whatever reason that SoC only got a B addition to the name, but major changes internally - likely it is pin compatible with the non-b-variant. Other change is actually exporting PCIe pipe-clocks that were already in the binding. * tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3568: Add PCIe pipe clock gates clk: rockchip: Add clock controller for the RV1103B dt-bindings: clock: rockchip: Add RV1103B CRU support
2026-04-11Merge tag 'renesas-clk-for-v7.1-tag2' of ↵Stephen Boyd13-33/+321
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add SPI clocks and resets on Renesas RZ/G3E - Add PCIe clocks and resets on Renesas RZ/V2N, RZ/V2H(P), and RZ/G3E - Enable watchdog reset on Renesas RZ/N1D - Remove clocks for watchdogs meant for other CPU cores on Renesas RZ/V2N - Handle critical clock during system resume on Renesas RZ/G2L, RZ/G2UL, and RZ/G3S - Add initial support for the Renesas RZ/G3L (R9A08G046) SoC * tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Add support for RZ/G3L SoC dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC clk: renesas: rzg2l: Re-enable critical module clocks during resume clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper() clk: renesas: rzg2l: Add helper for mod clock enable/disable clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries clk: renesas: rzg2l: Add support for critical resets clk: renesas: r9a09g056: Remove entries for WDT{0,2,3} clk: renesas: r9a06g032: Enable watchdog reset sources clk: renesas: cpg-mssr: Use struct_size() helper clk: renesas: r9a09g047: Add PCIe clocks and reset clk: renesas: r9a09g057: Add PCIe clocks and reset clk: renesas: r9a09g056: Add PCIe clocks and reset clk: renesas: r9a09g047: Add entries for the RSPIs
2026-04-11Merge tag 'tenstorrent-clk-for-v7.1' of ↵Stephen Boyd5-0/+889
git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux into clk-tenstorrent Pull Tenstorrent clk driver updates from Drew Fustini: - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC * tag 'tenstorrent-clk-for-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux: clk: tenstorrent: Add Atlantis clock controller driver reset: tenstorrent: Add reset controller for Atlantis dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu
2026-04-08clk: qcom: gcc: Add multiple global clock controller driver for Nord SoCTaniya Das6-0/+6197
The global clock controller on the Nord SoC is partitioned into GCC, SE_GCC, NE_GCC, and NW_GCC. Introduce driver support for each of these controllers. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> [Shawn: Drop include of <linux/of.h> as the driver doesn't use any OF APIs] Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260403-nord-clks-v1-6-018af14979fd@oss.qualcomm.com [bjorn: Added missing .use_rpm to gcc_nord_desc] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-08clk: qcom: rpmh: Add support for Nord rpmh clocksPrasanna Tolety1-0/+20
Add RPMH clock support for the Nord SoC to allow enable/disable of the clocks. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260403-nord-clks-v1-5-018af14979fd@oss.qualcomm.com [bjorn: sorted clk_rpmh_match_table[] addition] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-08clk: qcom: Add TCSR clock driver for Nord SoCTaniya Das3-0/+345
Add a clock driver for the TCSR clock controller found on Nord SoC, which provides refclks for PCIE, USB, SGMII, UFS subsystems. [Shawn: - Use compatible qcom,nord-tcsrcc - Drop include of <linux/of.h> as the driver doesn't use any OF APIs] Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260403-nord-clks-v1-4-018af14979fd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-05clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ONJagadeesh Kona1-0/+1
In Hamoa, SMMU invalidation requires the GCC_AGGRE_USB_NOC_AXI_CLK to be on for the USB QTB to be functional. This is currently explicitly enabled by the DWC3 glue driver, so an invalidation happening while the USB controller is suspended will fault. Solve this by voting for the GCC MMU USB QTB clock. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260327-hamoa-usb-qtb-clk-always-on-v2-1-7d8a406e650f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-05clk: qcom: Constify list of critical CBCR registersKrzysztof Kozlowski32-33/+33
The static array 'xxx_critical_cbcrs' contains probe match-like data and is not modified: neither by the driver defining it nor by common.c code using it. Make it const for code safety and code readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260331091721.61613-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-05clk: qcom: Constify qcom_cc_driver_dataKrzysztof Kozlowski33-33/+33
The static 'struct qcom_cc_driver_data' contains probe match-like data and is not modified: neither by the driver defining it nor by common.c code using it. Make it const for code safety and code readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260331091721.61613-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-05clk: qcom: videocc-glymur: Constify qcom_cc_descKrzysztof Kozlowski1-1/+1
Static 'struct qcom_cc_desc' is not modified by drivers and can be made const for code safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260331085521.37337-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-04-01clk: spear: fix resource leak in clk_register_vco_pll()Haoxiang Li1-1/+3
Add a goto label in clk_register_vco_pll(), unregister vco_clk if tpll_clk is failed to be registered. Signed-off-by: Haoxiang Li <lihaoxiang@isrc.iscas.ac.cn> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20260325062204.169648-1-lihaoxiang@isrc.iscas.ac.cn Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-03-30clk: qcom: Add a driver for SM8750 GPU clocksKonrad Dybcio4-0/+484
Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-2-78292b40b053@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC supportJohn Crispin1-0/+8
The CMN PLL in IPQ8074 SoC supplies fixed clocks to the networking subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20260311183942.10134-5-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC supportJohn Crispin1-0/+8
The CMN PLL in IPQ6018 SoC supplies fixed clocks to the networking subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20260311183942.10134-3-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-30clk: qcom: gdsc: Fix error path on registration of multiple pm subdomainsVladimir Zapolskiy1-1/+11
Some pm subdomains may be left in added to a parent domain state, if gdsc_add_subdomain_list() function fails in the middle and bails from a GDSC power domain controller registration out. Fixes: b489235b4dc0 ("clk: qcom: Support attaching GDSCs to multiple parents") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Link: https://lore.kernel.org/r/20260328012619.832770-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-26Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-2/+1
Cross-merge networking fixes after downstream PR (net-7.0-rc6). No conflicts, or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-26clk: renesas: Add support for RZ/G3L SoCBiju Das5-1/+167
The clock structure for RZ/G3L is almost identical to that of the RZ/G3S SoC with more IP blocks such as LCDC, CRU, LVDS, and GPU. Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and bind it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260324114329.268249-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-26clk: renesas: rzg2l: Re-enable critical module clocks during resumeBiju Das1-3/+18
After a suspend/resume cycle, critical module clocks (CLK_IS_CRITICAL) may be left disabled as there is no owning driver to restore them, unlike regular clocks. Add rzg2l_mod_enable_crit_clock_init_mstop() which walks all module clocks on resume, re-enables any critical clock found disabled, and then restores the MSTOP state for clocks that have one via the existing helper. This replaces the direct call to rzg2l_mod_clock_init_mstop() in rzg2l_cpg_resume(), preserving the correct clock-before-MSTOP restore ordering. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260324114329.268249-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-26clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()Biju Das1-9/+15
Refactor the mstop initialisation logic in rzg2l_mod_clock_init_mstop() into a dedicated helper function rzg2l_mod_clock_init_mstop_helper(). This decouples the logic for setting module stop state on disabled clocks from the iteration loop, allowing it to be reused during resume to re-enable critical clocks. No functional change. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260324114329.268249-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-03-26clk: renesas: rzg2l: Add helper for mod clock enable/disableBiju Das1-3/+11