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Age	Commit message (Expand)	Author	Files	Lines
6 days	Merge branches 'clk-renesas', 'clk-samsung', 'clk-starfive', 'clk-tenstorrent...	Brian Masney	23	-174/+1155
2026-09-28	clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS	Wolfram Sang	1	-0/+3
2026-09-24	clk: renesas: rzg2l: Fix internal clock names	Geert Uytterhoeven	3	-15/+15
2026-09-24	clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets	Biju Das	1	-0/+10
2026-09-24	clk: renesas: Add support for RZ/G2M v3.0	Ayman Chaudhry	5	-0/+181
2026-09-24	clk: renesas: r9a08g046: Add CANFD clocks and resets	Biju Das	1	-0/+9
2026-09-24	clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks	Biju Das	1	-2/+4
2026-09-23	clk: renesas: convert drivers over to use subsys_platform_driver()	Brian Masney	4	-25/+4
2026-09-21	clk: renesas: r8a779g0: Add ZG clocks	Kuninori Morimoto	1	-0/+2
2026-09-21	clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()	Kuninori Morimoto	6	-26/+33
2026-09-14	clk: renesas: r9a09g077: Register SYSC regmap	Lad Prabhakar	4	-0/+148
2026-09-09	clk: renesas: rcar-gen3: Use FIELD_GET()	Geert Uytterhoeven	2	-8/+10
2026-09-07	clk: renesas: rzv2h: Convert to clk_hw based provider API	John Madieu	1	-84/+69
2026-09-07	clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_re...	John Madieu	1	-3/+0
2026-09-07	clk: renesas: r9a08g046: Add PCIe clocks and reset	Biju Das	1	-0/+9
2026-09-01	clk: renesas: Make sure clk_init_data is fully initialized	Geert Uytterhoeven	2	-13/+13
2026-08-31	clk: renesas: r9a08g046: Add clock and reset entries for LVDS	Biju Das	1	-0/+5
2026-08-31	clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries	Biju Das	1	-0/+62
2026-08-31	clk: renesas: r9a08g046: Sort macro definitions alphabetically	Biju Das	1	-8/+8
2026-08-31	clk: renesas: rzg2l: Add support for RZ/G3L DSI mux	Biju Das	2	-0/+94
2026-08-31	clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty ...	Biju Das	2	-0/+93
2026-08-31	clk: renesas: rzg2l: Add support for divider flags	Biju Das	2	-7/+12
2026-08-31	clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flags	Biju Das	2	-15/+15
2026-08-31	clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3L	Biju Das	2	-0/+236
2026-08-31	clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3L	Biju Das	2	-0/+131
2026-08-31	clk: renesas: Clean-up simple provider misuse of the consumer API	Jerome Brunet	1	-1/+1
2026-08-20	Merge branches 'clk-pile' and 'clk-microchip' into clk-next	Stephen Boyd	1	-7/+1
2026-08-17	Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile	Stephen Boyd	1	-7/+1
2026-08-06	clk: renesas: Add R-Car X5H CPG driver	Geert Uytterhoeven	3	-0/+171
2026-08-05	Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3	Geert Uytterhoeven	4	-4/+0
2026-07-13	clk: r9a08g045: Add clocks and resets for CAN-FD	Claudiu Beznea	1	-0/+9
2026-07-03	Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c f...	Uwe Kleine-König (The Capable Hub)	4	-4/+0
2026-06-30	clk: renesas: r9a09g047: Add LVDS clocks and resets	Tommaso Merciai	1	-0/+11
2026-06-30	clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display p...	Lad Prabhakar	2	-0/+373
2026-06-30	clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library	Lad Prabhakar	4	-203/+222
2026-06-30	clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations	Lad Prabhakar	1	-4/+4
2026-06-30	clk: renesas: r9a08g046: Add USB2.0 clock and reset entries	Biju Das	1	-0/+15
2026-06-30	clk: renesas: r9a09g077: Add RTC clocks	Lad Prabhakar	1	-1/+3
2026-06-30	clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC ...	Lad Prabhakar	1	-2/+18
2026-06-30	clk: renesas: r9a08g046: Add clock and reset entries for GE3D	Biju Das	1	-0/+23
2026-06-30	clk: renesas: r9a08g046: Add clock and reset entries for SDHI	Biju Das	1	-0/+92
2026-06-30	clk: renesas: r9a09g047: Add audio clock and reset support	John Madieu	1	-1/+111
2026-06-29	clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()	Brian Masney	1	-7/+1
2026-05-28	clk: renesas: r9a08g045: Drop unused pm_domain header file	Biju Das	1	-1/+0
2026-05-28	clk: renesas: r8a779g0: Add DSC clock	Marek Vasut	1	-0/+1
2026-05-25	clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing	Lad Prabhakar	1	-3/+3
2026-05-25	clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro	Lad Prabhakar	1	-7/+0
2026-05-22	clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones	Biju Das	1	-14/+12
2026-05-22	clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro	Biju Das	4	-15/+9
2026-05-22	clk: renesas: rzg2l: Simplify SAM PLL configuration macro	Biju Das	5	-16/+10