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Age	Commit message (Expand)	Author	Files	Lines
2025-12-08	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	12	-71/+1102
2025-11-24	clk: renesas: Use bitfield helpers	Geert Uytterhoeven	3	-19/+11
2025-11-13	clk: renesas: r9a09g077: Add SPI module clocks	Cosmin Tanislav	1	-1/+21
2025-11-13	clk: renesas: r9a09g056: Add USB3.0 clocks/resets	Lad Prabhakar	1	-1/+8
2025-11-13	clk: renesas: r9a09g057: Add USB3.0 clocks/resets	Lad Prabhakar	1	-1/+15
2025-11-13	clk: renesas: r9a09g047: Add RSCI clocks/resets	Biju Das	1	-0/+126
2025-11-12	clk: renesas: r9a06g032: Fix memory leak in error path	Haotian Zhang	1	-3/+3
2025-11-12	clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration	Lad Prabhakar	1	-14/+16
2025-11-12	clk: renesas: r9a09g077: Remove stray blank line	Lad Prabhakar	1	-1/+0
2025-11-12	clk: renesas: r9a09g077: Propagate rate changes to parent clocks	Lad Prabhakar	1	-2/+2
2025-11-12	clk: renesas: r8a779a0: Add 3DGE module clock	Niklas Söderlund	1	-0/+1
2025-11-10	clk: renesas: r8a779a0: Add ZG Core clock	Niklas Söderlund	1	-1/+5
2025-11-10	clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB	Niklas Söderlund	1	-2/+7
2025-10-27	clk: renesas: r9a09g056: Add clock and reset entries for ISP	Lad Prabhakar	1	-0/+14
2025-10-27	clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets	Lad Prabhakar	1	-0/+31
2025-10-27	clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules	Lad Prabhakar	1	-0/+64
2025-10-27	clk: renesas: r9a09g077: Add TSU module clock	Cosmin Tanislav	1	-0/+1
2025-10-27	clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC	Lad Prabhakar	2	-0/+65
2025-10-27	Merge tag 'clk-renesas-rzv2h-plldsi-tag' into renesas-clk-for-v6.19	Geert Uytterhoeven	2	-11/+527
2025-10-27	clk: renesas: rzv2h: Add support for DSI clocks	Lad Prabhakar	2	-2/+514
2025-10-27	clk: renesas: rzv2h: Use GENMASK for PLL fields	Lad Prabhakar	1	-7/+8
2025-10-27	clk: renesas: rzv2h: Add instance field to struct pll	Lad Prabhakar	1	-4/+7
2025-10-23	clk: renesas: r9a09g057: Add clock and reset entries for RTC	Ovidiu Panait	1	-0/+4
2025-10-23	clk: renesas: cpg-mssr: Spelling s/offets/offsets/	Geert Uytterhoeven	1	-1/+1
2025-10-23	clk: renesas: r9a09g057: Add clock and reset entries for TSU	Ovidiu Panait	1	-0/+6
2025-10-23	clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP	Lad Prabhakar	1	-2/+13
2025-10-20	clk: renesas: cpg-mssr: Add module reset support for RZ/T2H	Lad Prabhakar	1	-4/+107
2025-10-14	clk: renesas: r9a09g057: Add clock and reset entries for ISP	Daniel Scally	2	-0/+16
2025-10-14	clk: renesas: r9a09g047: Add clock and reset entries for USB2	Tommaso Merciai	1	-1/+17
2025-10-14	clk: renesas: Use IS_ERR() for pointers that cannot be NULL	Geert Uytterhoeven	3	-3/+3
2025-10-14	clk: renesas: cpg-lib: Remove unneeded semicolon	Geert Uytterhoeven	1	-1/+1
2025-10-14	clk: renesas: r9a09g077: Add ADC module clocks	Cosmin Tanislav	1	-0/+3
2025-10-14	clk: renesas: cpg-mssr: Read back reset registers to assure values latched	Marek Vasut	1	-25/+21
2025-10-14	clk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callback	Marek Vasut	1	-2/+9
2025-09-12	clk: renesas: r9a09g05[67]: Reduce differences	Geert Uytterhoeven	2	-6/+5
2025-09-12	clk: renesas: r9a09g047: Add USB3.0 clocks/resets	Biju Das	1	-1/+8
2025-09-12	clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()	Yuan CHen	1	-2/+5
2025-09-11	clk: renesas: r9a09g056: Add clock and reset entries for I3C	Lad Prabhakar	1	-0/+8
2025-09-11	clk: renesas: r9a09g057: Add clock and reset entries for I3C	Lad Prabhakar	1	-0/+8
2025-09-04	clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks	Lad Prabhakar	1	-1/+13
2025-09-04	clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()	Tommaso Merciai	1	-2/+1
2025-09-04	clk: renesas: rzv2h: Re-assert reset on deassert timeout	Tommaso Merciai	1	-3/+10
2025-09-04	clk: renesas: rzg2l: Re-assert reset on deassert timeout	Tommaso Merciai	1	-2/+8
2025-09-04	clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()	Tommaso Merciai	1	-29/+15
2025-08-25	clk: renesas: r9a09g047: Add GPT clocks and resets	Biju Das	1	-0/+8
2025-08-20	clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5	Lad Prabhakar	1	-0/+25
2025-08-20	clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()	Brian Masney	1	-10/+0
2025-08-20	clk: renesas: rzg2l: convert from round_rate() to determine_rate()	Brian Masney	1	-5/+4
2025-08-20	clk: renesas: r9a07g04[34]: Use tabs instead of spaces	Claudiu Beznea	2	-8/+8
2025-08-20	clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL	Claudiu Beznea	1	-66/+66