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Age	Commit message (Expand)	Author	Files	Lines
2025-10-27	riscv: asm: use .insn for making custom instructions	Ben Dooks	1	-3/+3
2025-09-19	riscv: hwprobe: Add MIPS vendor extension probing	Aleksa Paunovic	1	-0/+22
2025-09-19	riscv: Add xmipsexectl instructions	Aleksa Paunovic	1	-0/+19
2025-09-18	riscv: Add xmipsexectl as a vendor extension	Aleksa Paunovic	1	-0/+18
2025-05-08	riscv: Add SiFive xsfvfwmaccqqq vendor extension	Cyan Yang	1	-0/+1
2025-05-08	riscv: Add SiFive xsfvfnrclipxfqf vendor extension	Cyan Yang	1	-0/+1
2025-05-08	riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod...	Cyan Yang	1	-0/+19
2025-05-08	riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions	Cyan Yang	1	-0/+14
2025-01-18	riscv: hwprobe: Add thead vendor extension probing	Charlie Jenkins	2	-0/+56
2025-01-18	riscv: Add xtheadvector instruction definitions	Charlie Jenkins	1	-0/+25
2025-01-18	riscv: vector: Use vlenb from DT for thead	Charlie Jenkins	1	-0/+6
2025-01-18	riscv: Add thead and xtheadvector as a vendor extension	Charlie Jenkins	1	-0/+16
2024-07-22	riscv: Extend cpufeature.c to detect vendor extensions	Charlie Jenkins	1	-0/+19