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dependabot/pip/drivers/gpu/drm/ci/xfails/certifi-2024.7.4
dependabot/pip/drivers/gpu/drm/ci/xfails/idna-3.7
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dependabot/pip/drivers/gpu/drm/ci/xfails/requests-2.32.2
dependabot/pip/drivers/gpu/drm/ci/xfails/setuptools-70.0.0
dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.0.7
dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.2.2
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arch
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riscv
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errata
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sifive
Age
Commit message (
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Author
Files
Lines
2024-11-07
asm-generic: introduce text-patching.h
Mike Rapoport (Microsoft)
1
-1
/
+1
2024-09-15
riscv: errata: sifive: Use SYM_*() assembly macros
Jisheng Zhang
1
-4
/
+4
2024-07-22
riscv: Extend cpufeature.c to detect vendor extensions
Charlie Jenkins
1
-0
/
+3
2024-04-29
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
Samuel Holland
1
-0
/
+5
2023-04-29
RISC-V: fix sifive and thead section mismatches in errata
Randy Dunlap
1
-5
/
+3
2023-04-28
Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-4
/
+4
2023-03-14
riscv: alternatives: Rename errata_id to patch_id
Andrew Jones
1
-3
/
+3
2023-03-14
riscv: alternatives: Remove unnecessary define and unused struct
Andrew Jones
1
-1
/
+1
2023-03-07
RISC-V: fix taking the text_mutex twice during sifive errata patching
Conor Dooley
1
-1
/
+1
2023-02-21
RISC-V: take text_mutex during alternative patching
Conor Dooley
1
-0
/
+3
2023-01-31
riscv: switch to relative alternative entries
Jisheng Zhang
1
-1
/
+2
2022-07-07
riscv: don't warn for sifive erratas in modules
Heiko Stuebner
1
-1
/
+2
2022-05-11
riscv: add memory-type errata for T-Head
Heiko Stuebner
1
-1
/
+6
2022-05-11
riscv: implement module alternatives
Heiko Stuebner
1
-5
/
+9
2022-05-11
riscv: allow different stages with alternatives
Heiko Stuebner
1
-1
/
+2
2021-06-01
riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled
Vincent
1
-1
/
+1
2021-04-26
riscv: sifive: Apply errata "cip-1200" patch
Vincent Chen
1
-0
/
+18
2021-04-26
riscv: sifive: Apply errata "cip-453" patch
Vincent Chen
3
-0
/
+59
2021-04-26
riscv: sifive: Add SiFive alternative ports
Vincent Chen
2
-0
/
+69