| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2025-12-08 | LoongArch: Adjust memory management for 32BIT/64BIT | Huacai Chen | 1 | -3/+0 |
| 2025-11-10 | LoongArch: Clarify 3 MSG interrupt features | Huacai Chen | 1 | -0/+2 |
| 2024-09-24 | LoongArch: Rework CPU feature probe from CPUCFG/IOCSR | Jiaxun Yang | 1 | -0/+2 |
| 2024-08-23 | LoongArch: Architectural preparation for AVEC irqchip | Huacai Chen | 1 | -0/+1 |
| 2023-06-29 | LoongArch: Introduce hardware page table walker | Huacai Chen | 1 | -1/+1 |
| 2023-04-18 | LoongArch: Fix probing of the CRC32 feature | Huacai Chen | 1 | -0/+1 |
| 2022-10-12 | LoongArch: Refactor cache probe and flush methods | Huacai Chen | 1 | -5/+0 |
| 2022-06-03 | LoongArch: Add CPU definition headers | Huacai Chen | 1 | -0/+73 |
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