diff options
Diffstat (limited to 'tools/arch')
| -rw-r--r-- | tools/arch/alpha/include/uapi/asm/errno.h | 2 | ||||
| -rw-r--r-- | tools/arch/arm64/include/asm/sysreg.h | 6 | ||||
| -rw-r--r-- | tools/arch/arm64/include/uapi/asm/kvm.h | 1 | ||||
| -rw-r--r-- | tools/arch/arm64/include/uapi/asm/unistd.h | 24 | ||||
| -rw-r--r-- | tools/arch/mips/include/uapi/asm/errno.h | 2 | ||||
| -rw-r--r-- | tools/arch/parisc/include/uapi/asm/errno.h | 2 | ||||
| -rw-r--r-- | tools/arch/sparc/include/uapi/asm/errno.h | 2 | ||||
| -rw-r--r-- | tools/arch/x86/include/asm/amd/ibs.h | 4 | ||||
| -rw-r--r-- | tools/arch/x86/include/asm/cpufeatures.h | 6 | ||||
| -rw-r--r-- | tools/arch/x86/include/asm/msr-index.h | 15 | ||||
| -rw-r--r-- | tools/arch/x86/include/asm/orc_types.h | 9 | ||||
| -rw-r--r-- | tools/arch/x86/include/uapi/asm/kvm.h | 9 | ||||
| -rw-r--r-- | tools/arch/x86/kcpuid/cpuid.csv | 671 |
13 files changed, 409 insertions, 344 deletions
diff --git a/tools/arch/alpha/include/uapi/asm/errno.h b/tools/arch/alpha/include/uapi/asm/errno.h index 3d265f6babaf..6791f6508632 100644 --- a/tools/arch/alpha/include/uapi/asm/errno.h +++ b/tools/arch/alpha/include/uapi/asm/errno.h @@ -55,6 +55,7 @@ #define ENOSR 82 /* Out of streams resources */ #define ETIME 83 /* Timer expired */ #define EBADMSG 84 /* Not a data message */ +#define EFSBADCRC EBADMSG /* Bad CRC detected */ #define EPROTO 85 /* Protocol error */ #define ENODATA 86 /* No data available */ #define ENOSTR 87 /* Device not a stream */ @@ -96,6 +97,7 @@ #define EREMCHG 115 /* Remote address changed */ #define EUCLEAN 117 /* Structure needs cleaning */ +#define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ #define ENOTNAM 118 /* Not a XENIX named type file */ #define ENAVAIL 119 /* No XENIX semaphores available */ #define EISNAM 120 /* Is a named type file */ diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h index 178b7322bf04..f75efe98e9df 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -847,12 +847,6 @@ #define SCTLR_ELx_A (BIT(1)) #define SCTLR_ELx_M (BIT(0)) -/* SCTLR_EL2 specific flags. */ -#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ - (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ - (BIT(29))) - -#define SCTLR_EL2_BT (BIT(36)) #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL2 SCTLR_ELx_EE #else diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h index a792a599b9d6..1c13bfa2d38a 100644 --- a/tools/arch/arm64/include/uapi/asm/kvm.h +++ b/tools/arch/arm64/include/uapi/asm/kvm.h @@ -428,6 +428,7 @@ enum { #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 +#define KVM_DEV_ARM_VGIC_USERSPACE_PPIS 5 /* Device Control API on vcpu fd */ #define KVM_ARM_VCPU_PMU_V3_CTRL 0 diff --git a/tools/arch/arm64/include/uapi/asm/unistd.h b/tools/arch/arm64/include/uapi/asm/unistd.h index df36f23876e8..9306726337fe 100644 --- a/tools/arch/arm64/include/uapi/asm/unistd.h +++ b/tools/arch/arm64/include/uapi/asm/unistd.h @@ -1,2 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#include <asm/unistd_64.h> +/* + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define __ARCH_WANT_RENAMEAT +#define __ARCH_WANT_NEW_STAT +#define __ARCH_WANT_SET_GET_RLIMIT +#define __ARCH_WANT_TIME32_SYSCALLS +#define __ARCH_WANT_MEMFD_SECRET + +#include <asm-generic/unistd.h> diff --git a/tools/arch/mips/include/uapi/asm/errno.h b/tools/arch/mips/include/uapi/asm/errno.h index 2fb714e2d6d8..c01ed91b1ef4 100644 --- a/tools/arch/mips/include/uapi/asm/errno.h +++ b/tools/arch/mips/include/uapi/asm/errno.h @@ -50,6 +50,7 @@ #define EDOTDOT 73 /* RFS specific error */ #define EMULTIHOP 74 /* Multihop attempted */ #define EBADMSG 77 /* Not a data message */ +#define EFSBADCRC EBADMSG /* Bad CRC detected */ #define ENAMETOOLONG 78 /* File name too long */ #define EOVERFLOW 79 /* Value too large for defined data type */ #define ENOTUNIQ 80 /* Name not unique on network */ @@ -88,6 +89,7 @@ #define EISCONN 133 /* Transport endpoint is already connected */ #define ENOTCONN 134 /* Transport endpoint is not connected */ #define EUCLEAN 135 /* Structure needs cleaning */ +#define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ #define ENOTNAM 137 /* Not a XENIX named type file */ #define ENAVAIL 138 /* No XENIX semaphores available */ #define EISNAM 139 /* Is a named type file */ diff --git a/tools/arch/parisc/include/uapi/asm/errno.h b/tools/arch/parisc/include/uapi/asm/errno.h index 8d94739d75c6..8cbc07c1903e 100644 --- a/tools/arch/parisc/include/uapi/asm/errno.h +++ b/tools/arch/parisc/include/uapi/asm/errno.h @@ -36,6 +36,7 @@ #define EDOTDOT 66 /* RFS specific error */ #define EBADMSG 67 /* Not a data message */ +#define EFSBADCRC EBADMSG /* Bad CRC detected */ #define EUSERS 68 /* Too many users */ #define EDQUOT 69 /* Quota exceeded */ #define ESTALE 70 /* Stale file handle */ @@ -62,6 +63,7 @@ #define ERESTART 175 /* Interrupted system call should be restarted */ #define ESTRPIPE 176 /* Streams pipe error */ #define EUCLEAN 177 /* Structure needs cleaning */ +#define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ #define ENOTNAM 178 /* Not a XENIX named type file */ #define ENAVAIL 179 /* No XENIX semaphores available */ #define EISNAM 180 /* Is a named type file */ diff --git a/tools/arch/sparc/include/uapi/asm/errno.h b/tools/arch/sparc/include/uapi/asm/errno.h index 81a732b902ee..4a41e7835fd5 100644 --- a/tools/arch/sparc/include/uapi/asm/errno.h +++ b/tools/arch/sparc/include/uapi/asm/errno.h @@ -48,6 +48,7 @@ #define ENOSR 74 /* Out of streams resources */ #define ENOMSG 75 /* No message of desired type */ #define EBADMSG 76 /* Not a data message */ +#define EFSBADCRC EBADMSG /* Bad CRC detected */ #define EIDRM 77 /* Identifier removed */ #define EDEADLK 78 /* Resource deadlock would occur */ #define ENOLCK 79 /* No record locks available */ @@ -91,6 +92,7 @@ #define ENOTUNIQ 115 /* Name not unique on network */ #define ERESTART 116 /* Interrupted syscall should be restarted */ #define EUCLEAN 117 /* Structure needs cleaning */ +#define EFSCORRUPTED EUCLEAN /* Filesystem is corrupted */ #define ENOTNAM 118 /* Not a XENIX named type file */ #define ENAVAIL 119 /* No XENIX semaphores available */ #define EISNAM 120 /* Is a named type file */ diff --git a/tools/arch/x86/include/asm/amd/ibs.h b/tools/arch/x86/include/asm/amd/ibs.h index cbce54fec7b9..d0777b597322 100644 --- a/tools/arch/x86/include/asm/amd/ibs.h +++ b/tools/arch/x86/include/asm/amd/ibs.h @@ -77,7 +77,7 @@ union ibs_op_data { __u64 val; struct { __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */ - tag_to_ret_ctr:16, /* 15-31: op tag to retire count */ + tag_to_ret_ctr:16, /* 16-31: op tag to retire count */ reserved1:2, /* 32-33: reserved */ op_return:1, /* 34: return op */ op_brn_taken:1, /* 35: taken branch op */ @@ -110,7 +110,7 @@ union ibs_op_data3 { __u64 ld_op:1, /* 0: load op */ st_op:1, /* 1: store op */ dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */ - dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */ + dc_l2tlb_miss:1, /* 3: data cache L2TLB miss in 2M page */ dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */ dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */ dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index c3b53beb1300..86d17b195e79 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -84,7 +84,7 @@ #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */ #define X86_FEATURE_BTS ( 3*32+13) /* "bts" Branch Trace Store */ #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* syscall in IA32 userspace */ -#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* sysenter in IA32 userspace */ +#define X86_FEATURE_SYSFAST32 ( 3*32+15) /* sysenter/syscall in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* "rep_good" REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* "amd_lbr_v2" AMD Last Branch Record Extension Version 2 */ #define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* Clear CPU buffers using VERW */ @@ -326,6 +326,7 @@ #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52[H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* "lam" Linear Address Masking */ +#define X86_FEATURE_MOVRS (12*32+31) /* MOVRS instructions */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ @@ -414,7 +415,7 @@ */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA overflow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error containment and recovery */ - +#define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ @@ -472,6 +473,7 @@ #define X86_FEATURE_GP_ON_USER_CPUID (20*32+17) /* User CPUID faulting */ #define X86_FEATURE_PREFETCHI (20*32+20) /* Prefetch Data/Instruction to Cache Level */ +#define X86_FEATURE_ERAPS (20*32+24) /* Enhanced Return Address Predictor Security */ #define X86_FEATURE_SBPB (20*32+27) /* Selective Branch Prediction Barrier */ #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */ #define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */ diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 3d0a0950d20a..6673601246b3 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -263,6 +263,11 @@ #define MSR_SNOOP_RSP_0 0x00001328 #define MSR_SNOOP_RSP_1 0x00001329 +#define MSR_OMR_0 0x000003e0 +#define MSR_OMR_1 0x000003e1 +#define MSR_OMR_2 0x000003e2 +#define MSR_OMR_3 0x000003e3 + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 @@ -735,7 +740,10 @@ #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) #define MSR_AMD64_SNP_SECURE_AVIC_BIT 18 #define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT) -#define MSR_AMD64_SNP_RESV_BIT 19 +#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19) +#define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT 23 +#define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT) +#define MSR_AMD64_SNP_RESV_BIT 24 #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT) #define MSR_AMD64_SAVIC_CONTROL 0xc0010138 #define MSR_AMD64_SAVIC_EN_BIT 0 @@ -794,8 +802,8 @@ #define MSR_F19H_UMC_PERF_CTR 0xc0010801 /* Zen 2 */ -#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 -#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) +#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 +#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT 1 /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 @@ -1219,6 +1227,7 @@ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 #define MSR_PERF_METRICS 0x00000329 diff --git a/tools/arch/x86/include/asm/orc_types.h b/tools/arch/x86/include/asm/orc_types.h index e0125afa53fb..5837c2bb277f 100644 --- a/tools/arch/x86/include/asm/orc_types.h +++ b/tools/arch/x86/include/asm/orc_types.h @@ -28,15 +28,16 @@ * and GCC realigned stacks. */ #define ORC_REG_UNDEFINED 0 -#define ORC_REG_PREV_SP 1 +#define ORC_REG_AX 1 #define ORC_REG_DX 2 -#define ORC_REG_DI 3 +#define ORC_REG_SP 3 #define ORC_REG_BP 4 -#define ORC_REG_SP 5 +#define ORC_REG_DI 5 #define ORC_REG_R10 6 #define ORC_REG_R13 7 -#define ORC_REG_BP_INDIRECT 8 +#define ORC_REG_PREV_SP 8 #define ORC_REG_SP_INDIRECT 9 +#define ORC_REG_BP_INDIRECT 10 #define ORC_REG_MAX 15 #define ORC_TYPE_UNDEFINED 0 diff --git a/tools/arch/x86/include/uapi/asm/kvm.h b/tools/arch/x86/include/uapi/asm/kvm.h index 7ceff6583652..0d4538fa6c31 100644 --- a/tools/arch/x86/include/uapi/asm/kvm.h +++ b/tools/arch/x86/include/uapi/asm/kvm.h @@ -476,6 +476,7 @@ struct kvm_sync_regs { #define KVM_X86_QUIRK_SLOT_ZAP_ALL (1 << 7) #define KVM_X86_QUIRK_STUFF_FEATURE_MSRS (1 << 8) #define KVM_X86_QUIRK_IGNORE_GUEST_PAT (1 << 9) +#define KVM_X86_QUIRK_VMCS12_ALLOW_FREEZE_IN_SMM (1 << 10) #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 @@ -503,6 +504,7 @@ struct kvm_sync_regs { #define KVM_X86_GRP_SEV 1 # define KVM_X86_SEV_VMSA_FEATURES 0 # define KVM_X86_SNP_POLICY_BITS 1 +# define KVM_X86_SEV_SNP_REQ_CERTS 2 struct kvm_vmx_nested_state_data { __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; @@ -743,6 +745,7 @@ enum sev_cmd_id { KVM_SEV_SNP_LAUNCH_START = 100, KVM_SEV_SNP_LAUNCH_UPDATE, KVM_SEV_SNP_LAUNCH_FINISH, + KVM_SEV_SNP_ENABLE_REQ_CERTS, KVM_SEV_NR_MAX, }; @@ -914,8 +917,10 @@ struct kvm_sev_snp_launch_finish { __u64 pad1[4]; }; -#define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) -#define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) +#define KVM_X2APIC_API_USE_32BIT_IDS _BITULL(0) +#define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK _BITULL(1) +#define KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST _BITULL(2) +#define KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST _BITULL(3) struct kvm_hyperv_eventfd { __u32 conn_id; diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv index 8d925ce9750f..9f5155c825ca 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.4 +# Generator: x86-cpuid-db v3.0 # # Auto-generated file. @@ -10,9 +10,9 @@ # LEAF, SUBLEAVES, reg, bits, short_name , long_description # Leaf 0H -# Maximum standard leaf number + CPU vendor string +# Maximum standard leaf + CPU vendor string - 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7 @@ -134,23 +134,23 @@ 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function) # Leaf 5H -# MONITOR/MWAIT instructions enumeration +# MONITOR/MWAIT instructions 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes - 0x5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported - 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported - 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT - 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT - 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT - 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT - 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT - 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT - 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT - 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT + 0x5, 0, ecx, 0, mwait_ext , MONITOR/MWAIT extensions + 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break event for MWAIT + 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states + 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states + 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states + 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states + 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states + 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states + 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states + 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states # Leaf 6H -# Thermal and Power Management enumeration +# Thermal and power management 0x6, 0, eax, 0, dtherm , Digital temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost @@ -158,24 +158,25 @@ 0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension 0x6, 0, eax, 6, pts , Package thermal management - 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported + 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers 0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR) - 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) 0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference 0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request - 0x6, 0, eax, 13, hdc_base_regs , HDC base registers are supported + 0x6, 0, eax, 13, hdc_base_regs , HDC base registers 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0 0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change 0x6, 0, eax, 16, hwp_peci_override , HWP PECI override 0x6, 0, eax, 17, hwp_flexible , Flexible HWP 0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode - 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported - 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported - 0x6, 0, eax, 23, thread_director , Intel thread director support - 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported + 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP request is supported + 0x6, 0, eax, 22, hwp_ctl , IA32_HWP_CTL MSR + 0x6, 0, eax, 23, thread_director , Intel thread director + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds 0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface) - 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support + 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting @@ -183,11 +184,11 @@ 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU hardware feedback interface index # Leaf 7H -# Extended CPU features enumeration +# Extended CPU features 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number of leaf 0x7 subleaves - 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support - 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported + 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR 0x7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions) 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1 0x7, 0, ebx, 4, hle , Hardware Lock Elision @@ -227,7 +228,7 @@ 0x7, 0, ecx, 7, cet_ss , CET shadow stack features 0x7, 0, ecx, 8, gfni , Galois field new instructions 0x7, 0, ecx, 9, vaes , Vector AES instructions - 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction 0x7, 0, ecx, 11, avx512_vnni , Vector neural network instructions 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms 0x7, 0, ecx, 13, tme , Intel total memory encryption @@ -235,34 +236,34 @@ 0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID instruction - 0x7, 0, ecx, 23, key_locker , Intel key locker support + 0x7, 0, ecx, 23, key_locker , Intel key locker 0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection 0x7, 0, ecx, 25, cldemote , CLDEMOTE instruction 0x7, 0, ecx, 27, movdiri , MOVDIRI instruction 0x7, 0, ecx, 28, movdir64b , MOVDIR64B instruction - 0x7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 29, enqcmd , Enqueue stores (ENQCMD{,S}) 0x7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration 0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages 0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision 0x7, 0, edx, 4, fsrm , Fast short REP MOV - 0x7, 0, edx, 5, uintr , CPU supports user interrupts + 0x7, 0, edx, 5, uintr , User interrupts 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available - 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR + 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts - 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit 0x7, 0, edx, 14, serialize , SERIALIZE instruction 0x7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part' 0x7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking 0x7, 0, edx, 18, pconfig , PCONFIG instruction 0x7, 0, edx, 19, arch_lbr , Intel architectural LBRs 0x7, 0, edx, 20, ibt , CET indirect branch tracking - 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions - 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support - 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support + 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture + 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer 0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions) 0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors 0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR @@ -273,7 +274,7 @@ 0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions 0x7, 1, eax, 6, lass , Linear address space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast short REP STOSB 0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB @@ -282,7 +283,7 @@ 0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations - 0x7, 1, eax, 22, hreset , History reset support + 0x7, 1, eax, 22, hreset , HRESET (Thread director history reset) 0x7, 1, eax, 23, avx_ifma , Integer fused multiply add 0x7, 1, eax, 26, lam , Linear address masking 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions @@ -298,35 +299,40 @@ 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S 0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed - 0x7, 2, edx, 6, uclock_disable , UC-lock disable is supported + 0x7, 2, edx, 6, uclock_disable , UC-lock disable # Leaf 9H -# Intel DCA (Direct Cache Access) enumeration +# Intel DCA (Direct Cache Access) 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS # Leaf AH -# Intel PMU (Performance Monitoring Unit) enumeration +# Intel PMU (Performance Monitoring Unit) 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID - 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of general PMU counters per logical CPU - 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of leaf 0xa EBX bit vector - 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available - 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available - 0xa, 0, ebx, 2, no_refcycle_evt , Reference cycles event not available - 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available - 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available - 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch instruction retired event not available - 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mispredict retired event not available - 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available + 0xa, 0, eax, 15:8, num_counters_gp , Number of general-purpose PMU counters per logical CPU + 0xa, 0, eax, 23:16, bit_width_gp , Bitwidth of PMU general-purpose counters + 0xa, 0, eax, 31:24, events_mask_len , Length of CPUID(0xa).EBX bit vector + 0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available + 0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available + 0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available + 0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available + 0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available + 0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available + 0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available + 0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available + 0xa, 0, ebx, 8, no_backend_bound , Topdown backend bound not available + 0xa, 0, ebx, 9, no_bad_speculation , Topdown bad speculation not available + 0xa, 0, ebx, 10, no_frontend_bound , Topdown frontend bound not available + 0xa, 0, ebx, 11, no_retiring , Topdown retiring not available + 0xa, 0, ebx, 12, no_lbr_inserts , LBR inserts not available 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap - 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters - 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters - 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation + 0xa, 0, edx, 4:0, num_counters_fixed , Number of fixed PMU counters + 0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth of PMU fixed counters + 0xa, 0, edx, 15, anythread_deprecation , AnyThread mode deprecation # Leaf BH -# CPUs v1 extended topology enumeration +# CPU extended topology v1 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain @@ -335,107 +341,109 @@ 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU # Leaf DH -# Processor extended state enumeration - - 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported - 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported - 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU registers) - 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U (bit 11) supported (CET user state) - 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S (bit 12) supported (CET supervisor state) - 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) - 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRSTOR area byte size, for XCR0 enabled features +# CPU extended state + + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 + 0xd, 0, eax, 1, xcr0_sse , XCR0.SSE + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS: MPX BND0-BND3 registers + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK: AVX-512 k0-k7 registers + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 registers + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 registers + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU: XSAVE PKRU registers + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U: CET user state + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S: CET supervisor state + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG: AMX can manage TILECONFIG + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA: AMX can manage TILEDATA + 0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XRSTOR area byte size, for XCR0 enabled features 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTOR area max byte size, all CPU features - 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling) + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP: Light-weight Profiling 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction 0xd, 1, eax, 1, xsavec , XSAVEC instruction 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR) - 0xd, 1, eax, 4, xfd , Extended feature disable support - 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled - 0xd, 1, ecx, 8, xss_pt , PT state, supported - 0xd, 1, ecx, 10, xss_pasid , PASID state, supported - 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported - 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported - 0xd, 1, ecx, 13, xss_hdc , HDC state, supported - 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported - 0xd, 1, ecx, 15, xss_lbr , LBR state, supported - 0xd, 1, ecx, 16, xss_hwp , HWP state, supported - 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes - 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes - 0xd, 63:2, ecx, 0, i |