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efine SET_TX_DESC_RSVD_MACID(__pdesc, __val) \ SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val) #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val) #define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) #define SET_TX_DESC_OWN_MAC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val) /* Dword 3 */ #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val) #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val) #define SET_TX_DESC_SEQ(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val) #define SET_TX_DESC_FRAG(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val) /* Dword 4 */ #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val) #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val) #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val) #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val) #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val) #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val) #define SET_TX_DESC_TXHT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val) #define SET_TX_DESC_TX_SHORT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val) #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val) #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val) #define SET_TX_DESC_TX_STBC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val) #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val) #define SET_TX_DESC_RTS_HT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val) #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val) #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val) #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val) #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val) #define SET_TX_DESC_USER_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val) /* Dword 5 */ #define SET_TX_DESC_PACKET_ID(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val) #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val) #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val) #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val) #define SET_TX_DESC_TX_AGC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val) /* Dword 6 */ #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val) #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val) /* Dword 7 */ #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val) #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val) #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val) /* Dword 8 */ #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val) #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32) /* Dword 9 */ #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val) /* Because the PCI Tx descriptors are chaied at the * initialization and all the NextDescAddresses in * these descriptors cannot not be cleared (,or * driver/HW cannot find the next descriptor), the * offset 36 (NextDescAddresses) is reserved when * the desc is cleared. */ #define TX_DESC_NEXT_DESC_OFFSET 36 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) /* Rx Desc */ #define RX_STATUS_DESC_SIZE 24 #define RX_DRV_INFO_SIZE_UNIT 8 /* DWORD 0 */ #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val) #define SET_RX_STATUS_DESC_ICV(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val) #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val) #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val) #define SET_RX_STATUS_DESC_QOS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val) #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) #define SET_RX_STATUS_DESC_EOR(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) #define SET_RX_STATUS_DESC_OWN(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 0, 14) #define GET_RX_STATUS_DESC_CRC32(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 14, 1) #define GET_RX_STATUS_DESC_ICV(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 15, 1) #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 16, 4) #define GET_RX_STATUS_DESC_SECURITY(__pdesc) \ SHIFT_AND_M