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)->num_def_rx_descs) #define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size) #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].max_txqs) #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].num_txqs) #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].max_rxqs) #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].num_rxqs) #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].num_rx_descs) #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].num_tx_descs) #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].rx_buf_size) #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].base_queue) #define CFG_GET_GMXID_NIC_IF(cfg, idx) \ ((cfg)->nic_if_cfg[idx].gmx_port_id) #define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp) #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \ ((cfg)->misc.host_link_query_interval) #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \ ((cfg)->misc.oct_link_query_interval) #define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp) #define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \ ((cfg)->nic_if_cfg[idx].num_rx_descs = value) #define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \ ((cfg)->nic_if_cfg[idx].num_tx_descs = value) /* Max IOQs per OCTEON Link */ #define MAX_IOQS_PER_NICIF 64 enum lio_card_type { LIO_210SV = 0, /* Two port, 66xx */ LIO_210NV, /* Two port, 68xx */ LIO_410NV, /* Four port, 68xx */ LIO_23XX /* 23xx */ }; #define LIO_210SV_NAME "210sv" #define LIO_210NV_NAME "210nv" #define LIO_410NV_NAME "410nv" #define LIO_23XX_NAME "23xx" /** Structure to define the configuration attributes for each Input queue. * Applicable to all Octeon processors **/ struct octeon_iq_config { #ifdef __BIG_ENDIAN_BITFIELD u64 reserved:16; /** Tx interrupt packets. Applicable to 23xx only */ u64 iq_intr_pkt:16; /** Minimum ticks to