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ister without effecting the mask state of other bits (0 = no effect). ==============================================*/ ACX_REG_HINT_MASK_SET, /*============================================= Host Interrupt Mask Clear 16bit,(Write only) ------------------------------------------ Setting a bit in this register clears the corresponding bin in ACX_HINT_MASK register without effecting the mask state of other bits (0 = no effect). =============================================*/ ACX_REG_HINT_MASK_CLR, /*============================================= Host Interrupt Status Nondestructive Read 16bit,(Read only) ------------------------------------------ The host can read this register to determine which interrupts are active. Reading this register doesn't effect its content. =============================================*/ ACX_REG_INTERRUPT_NO_CLEAR, /*============================================= Host Interrupt Status Clear on Read Register 16bit,(Read only) ------------------------------------------ The host can read this register to determine which interrupts are active. Reading this register clears it, thus making all interrupts inactive. ==============================================*/ ACX_REG_INTERRUPT_CLEAR, /*============================================= Host Interrupt Acknowledge Register 16bit,(Write only) ------------------------------------------ The host can set individual bits in this register to clear (acknowledge) the corresp. interrupt status bits in the HINT_STS_CLR and HINT_STS_ND registers, thus making the assotiated interrupt inactive. (0-no effect) ==============================================*/ ACX_REG_INTERRUPT_ACK, /*=============================================== Host Software Reset - 32bit RW ------------------------------------------ [31:1] Reserved 0 SOFT_RESET Soft Reset - When this bit is set, it holds the Wlan hardware in a soft reset state. This r