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path: root/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
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Diffstat (limited to 'drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c')
-rw-r--r--drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c67
1 files changed, 27 insertions, 40 deletions
diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
index 7fac1c2ba8e0..d6369eb7b570 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
@@ -19,13 +19,12 @@ static u32 phy_CalculateBitShift(u32 BitMask)
u32 i;
for (i = 0; i <= 31; i++) {
- if (((BitMask>>i) & 0x1) == 1)
+ if (((BitMask >> i) & 0x1) == 1)
break;
}
return i;
}
-
/**
* PHY_QueryBBReg_8723B - Read "specific bits" from BB register.
* @Adapter:
@@ -46,10 +45,8 @@ u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
BitShift = phy_CalculateBitShift(BitMask);
return (OriginalValue & BitMask) >> BitShift;
-
}
-
/**
* PHY_SetBBReg_8723B - Write "Specific bits" to BB register (page 8~).
* @Adapter:
@@ -80,10 +77,8 @@ void PHY_SetBBReg_8723B(
}
rtw_write32(Adapter, RegAddr, Data);
-
}
-
/* */
/* 2. RF register R/W API */
/* */
@@ -109,18 +104,18 @@ static u32 phy_RFSerialRead_8723B(
NewOffset = Offset;
if (eRFPath == RF_PATH_A) {
- tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
- tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
- PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
+ tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
+ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
} else {
- tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
- tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
- PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
+ tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */
+ PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
}
- tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
- PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
- PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
+ tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
+ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
udelay(10);
@@ -129,19 +124,18 @@ static u32 phy_RFSerialRead_8723B(
udelay(10);
if (eRFPath == RF_PATH_A)
- RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
+ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT(8));
else if (eRFPath == RF_PATH_B)
- RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
+ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT(8));
if (RfPiEnable) {
/* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
- retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
+ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
} else {
/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
- retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
+ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
}
return retValue;
-
}
/**
@@ -203,14 +197,13 @@ static void phy_RFSerialWrite_8723B(
/* */
/* Put write addr in [5:0] and write data in [31:16] */
/* */
- DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */
+ DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
/* */
/* Write Operation */
/* */
PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
}
-
/**
* PHY_QueryRFReg_8723B - Query "Specific bits" to RF register (page 8~).
* @Adapter:
@@ -266,18 +259,16 @@ void PHY_SetRFReg_8723B(
if (BitMask != bRFRegOffsetMask) {
Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
- Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
+ Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
}
phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
}
-
/* */
/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
/* */
-
/*-----------------------------------------------------------------------------
* PHY_MACConfig8192C - Config MAC by header file or parameter file.
*
@@ -329,7 +320,6 @@ static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
-
}
static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
@@ -373,7 +363,6 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
return _SUCCESS;
}
-
int PHY_BBConfig8723B(struct adapter *Adapter)
{
int rtStatus = _SUCCESS;
@@ -385,19 +374,20 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
/* Enable BB and RF */
RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
- rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
+ rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1)));
rtw_write32(Adapter, 0x948, 0x280); /* Others use Antenna S1 */
- rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
+ rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
msleep(1);
PHY_SetRFReg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
- rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
+ rtw_write8(Adapter, REG_SYS_FUNC_EN,
+ FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
/* */
/* Config BB and AGC */
@@ -531,7 +521,7 @@ u8 PHY_GetTxPowerIndex(
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
s8 txPower = 0, powerDiffByRate = 0, limit = 0;
- txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
+ txPower = (s8)PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, Rate);
limit = phy_get_tx_pwr_lmt(
@@ -551,7 +541,7 @@ u8 PHY_GetTxPowerIndex(
if (txPower > MAX_POWER_INDEX)
txPower = MAX_POWER_INDEX;
- return (u8) txPower;
+ return (u8)txPower;
}
void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)
@@ -584,7 +574,7 @@ static void phy_SetRegBW_8723B(
break;
case CHANNEL_WIDTH_40:
- u2tmp = RegRfMod_BW | BIT7;
+ u2tmp = RegRfMod_BW | BIT(7);
rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
break;
@@ -613,7 +603,6 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
u8 SubChnlNum = 0;
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
-
/* 3 Set Reg668 Reg440 BW */
phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
@@ -631,7 +620,7 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
- PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
+ PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT(31) | BIT(30)), 0x0);
break;
/* 40 MHz channel*/
@@ -641,11 +630,11 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
/* Set Control channel to upper or lower. These settings are required only for 40MHz */
- PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
+ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
- PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
+ PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break;
default:
break;
@@ -724,13 +713,11 @@ static void PHY_HandleSwChnlAndSetBW8723B(
if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
return;
-
if (pHalData->bSwChnl) {
pHalData->CurrentChannel = ChannelNum;
pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
}
-
if (pHalData->bSetChnlBW) {
pHalData->CurrentChannelBW = ChnlWidth;
pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
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