diff options
| -rw-r--r-- | sound/soc/fsl/fsl_asrc.c | 16 | ||||
| -rw-r--r-- | sound/soc/fsl/fsl_asrc.h | 14 |
2 files changed, 30 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index 2fe25667c888..5fda9b647c70 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -106,6 +106,12 @@ static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = { }, }; +static unsigned char clk_map_imx952[ASRC_CLK_MAP_LEN] = { + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, + 0x0, 0x1, 0x2, 0x3, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x4, 0x5, 0x6, 0x8, 0xf, 0xf, + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0x9, 0xa, 0xb, 0xc, 0xd, 0xf, 0xf, 0xf, 0xf, +}; + /* * According to RM, the divider range is 1 ~ 8, * prescaler is power of 2 from 1 ~ 128. @@ -1337,6 +1343,9 @@ static int fsl_asrc_probe(struct platform_device *pdev) asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; } + } else if (of_device_is_compatible(np, "fsl,imx952-asrc")) { + asrc_priv->clk_map[IN] = clk_map_imx952; + asrc_priv->clk_map[OUT] = clk_map_imx952; } asrc->channel_avail = 10; @@ -1575,11 +1584,18 @@ static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = { .channel_bits = 4, }; +static const struct fsl_asrc_soc_data fsl_asrc_imx952_data = { + .use_edma = true, + .channel_bits = 4, + .start_before_dma = true, +}; + static const struct of_device_id fsl_asrc_ids[] = { { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, + { .compatible = "fsl,imx952-asrc", .data = &fsl_asrc_imx952_data }, {} }; MODULE_DEVICE_TABLE(of, fsl_asrc_ids); diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h index 60b6865ca952..7a81366a0ee4 100644 --- a/sound/soc/fsl/fsl_asrc.h +++ b/sound/soc/fsl/fsl_asrc.h @@ -326,6 +326,13 @@ enum asrc_inclk { INCLK_SAI6_TX_BCLK = 0x22, INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, + + INCLK_SAI2_TX_BCLK = 0x26, + INCLK_SAI3_TX_BCLK = 0x27, + INCLK_SAI4_RX_BCLK = 0x28, + INCLK_SAI4_TX_BCLK = 0x29, + INCLK_SAI5_RX_BCLK = 0x2a, + INCLK_SAI5_TX_BCLK = 0x2b, }; enum asrc_outclk { @@ -366,6 +373,13 @@ enum asrc_outclk { OUTCLK_SAI6_TX_BCLK = 0x22, OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, + + OUTCLK_SAI2_TX_BCLK = 0x26, + OUTCLK_SAI3_TX_BCLK = 0x27, + OUTCLK_SAI4_RX_BCLK = 0x28, + OUTCLK_SAI4_TX_BCLK = 0x29, + OUTCLK_SAI5_RX_BCLK = 0x2a, + OUTCLK_SAI5_TX_BCLK = 0x2b, }; #define ASRC_CLK_MAX_NUM 16 |