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| author | Manikanta Maddireddy <mmaddireddy@nvidia.com> | 2026-04-10 11:55:07 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-05-12 16:01:11 -0500 |
| commit | 1e1b554c2b910591aa3fffdb8077a2ca33bf3cb2 (patch) | |
| tree | 024e659056dc65ba30376b74def24958748f9569 /tools | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
PCI: dwc: Apply ECRC workaround for DesignWare cores prior to 5.10a
The ECRC (TLP digest) workaround was originally applied only for DesignWare
core version 4.90a. Per discussion in Synopsys case, the dependency of the
iATU TD bit on ECRC generation was removed in 5.10a, so apply the
workaround for all DWC versions below that release.
Replace the misleading comment that referred to raw version constants
with readable DesignWare release name to help readability.
Fixes: b210b1595606 ("PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well")
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
[mani: corrected fixes tag format]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260410062507.657453-1-mmaddireddy@nvidia.com
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions