diff options
| author | Ahmed S. Darwish <darwi@linutronix.de> | 2026-03-27 03:15:17 +0100 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2026-03-28 17:28:35 +0100 |
| commit | 124ad3034ec0029b65178f3ab8a6cdca5a0b0519 (patch) | |
| tree | e24586448079313ba17d52448a93fce289e35564 /tools | |
| parent | 7f78e0b46e9984e955cb73ffada8dace8b4dd059 (diff) | |
tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0
Update kcpuid's CSV to version 3.0, as generated by x86-cpuid-db.
Summary of the v2.5 changes:
- Reduce the verbosity of leaf and bitfields descriptions, as formerly
requested by Boris.
- Leaf 0x8000000a: Add Page Modification Logging (PML) bit.
Summary of the v3.0 changes:
- Leaf 0x23: Introduce subleaf 2, Auto Counter Reload (ACR)
- Leaf 0x23: Introduce subleaf 4/5, PEBS capabilities and counters
- Leaf 0x1c: Return LBR depth as a bitmask instead of individual bits
- Leaf 0x0a: Use more descriptive PMU bitfield names
- Leaf 0x0a: Add various missing PMU events
- Leaf 0x06: Add missing IA32_HWP_CTL flag
- Leaf 0x0f: Add missing non-CPU (IO) Intel RDT bits
Thanks to Dave Hansen for reporting multiple missing bits.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.5/CHANGELOG.rst
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.rst
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/arch/x86/kcpuid/cpuid.csv | 671 |
1 files changed, 347 insertions, 324 deletions
diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv index 8d925ce9750f..9f5155c825ca 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.4 +# Generator: x86-cpuid-db v3.0 # # Auto-generated file. @@ -10,9 +10,9 @@ # LEAF, SUBLEAVES, reg, bits, short_name , long_description # Leaf 0H -# Maximum standard leaf number + CPU vendor string +# Maximum standard leaf + CPU vendor string - 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7 @@ -134,23 +134,23 @@ 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function) # Leaf 5H -# MONITOR/MWAIT instructions enumeration +# MONITOR/MWAIT instructions 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes - 0x5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported - 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported - 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT - 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT - 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT - 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT - 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT - 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT - 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT - 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT + 0x5, 0, ecx, 0, mwait_ext , MONITOR/MWAIT extensions + 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break event for MWAIT + 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states + 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states + 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states + 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states + 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states + 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states + 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states + 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states # Leaf 6H -# Thermal and Power Management enumeration +# Thermal and power management 0x6, 0, eax, 0, dtherm , Digital temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost @@ -158,24 +158,25 @@ 0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension 0x6, 0, eax, 6, pts , Package thermal management - 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported + 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers 0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR) - 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) 0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference 0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request - 0x6, 0, eax, 13, hdc_base_regs , HDC base registers are supported + 0x6, 0, eax, 13, hdc_base_regs , HDC base registers 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0 0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change 0x6, 0, eax, 16, hwp_peci_override , HWP PECI override 0x6, 0, eax, 17, hwp_flexible , Flexible HWP 0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode - 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported - 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported - 0x6, 0, eax, 23, thread_director , Intel thread director support - 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported + 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP request is supported + 0x6, 0, eax, 22, hwp_ctl , IA32_HWP_CTL MSR + 0x6, 0, eax, 23, thread_director , Intel thread director + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds 0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface) - 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support + 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting @@ -183,11 +184,11 @@ 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU hardware feedback interface index # Leaf 7H -# Extended CPU features enumeration +# Extended CPU features 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number of leaf 0x7 subleaves - 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support - 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported + 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR 0x7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions) 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1 0x7, 0, ebx, 4, hle , Hardware Lock Elision @@ -227,7 +228,7 @@ 0x7, 0, ecx, 7, cet_ss , CET shadow stack features 0x7, 0, ecx, 8, gfni , Galois field new instructions 0x7, 0, ecx, 9, vaes , Vector AES instructions - 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction 0x7, 0, ecx, 11, avx512_vnni , Vector neural network instructions 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms 0x7, 0, ecx, 13, tme , Intel total memory encryption @@ -235,34 +236,34 @@ 0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID instruction - 0x7, 0, ecx, 23, key_locker , Intel key locker support + 0x7, 0, ecx, 23, key_locker , Intel key locker 0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection 0x7, 0, ecx, 25, cldemote , CLDEMOTE instruction 0x7, 0, ecx, 27, movdiri , MOVDIRI instruction 0x7, 0, ecx, 28, movdir64b , MOVDIR64B instruction - 0x7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 29, enqcmd , Enqueue stores (ENQCMD{,S}) 0x7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration 0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages 0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision 0x7, 0, edx, 4, fsrm , Fast short REP MOV - 0x7, 0, edx, 5, uintr , CPU supports user interrupts + 0x7, 0, edx, 5, uintr , User interrupts 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available - 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR + 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts - 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit 0x7, 0, edx, 14, serialize , SERIALIZE instruction 0x7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part' 0x7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking 0x7, 0, edx, 18, pconfig , PCONFIG instruction 0x7, 0, edx, 19, arch_lbr , Intel architectural LBRs 0x7, 0, edx, 20, ibt , CET indirect branch tracking - 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions - 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support - 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support + 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture + 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer 0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions) 0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors 0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR @@ -273,7 +274,7 @@ 0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions 0x7, 1, eax, 6, lass , Linear address space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast short REP STOSB 0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB @@ -282,7 +283,7 @@ 0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations - 0x7, 1, eax, 22, hreset , History reset support + 0x7, 1, eax, 22, hreset , HRESET (Thread director history reset) 0x7, 1, eax, 23, avx_ifma , Integer fused multiply add 0x7, 1, eax, 26, lam , Linear address masking 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions @@ -298,35 +299,40 @@ 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S 0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed - 0x7, 2, edx, 6, uclock_disable , UC-lock disable is supported + 0x7, 2, edx, 6, uclock_disable , UC-lock disable # Leaf 9H -# Intel DCA (Direct Cache Access) enumeration +# Intel DCA (Direct Cache Access) 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS # Leaf AH -# Intel PMU (Performance Monitoring Unit) enumeration +# Intel PMU (Performance Monitoring Unit) 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID - 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of general PMU counters per logical CPU - 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of leaf 0xa EBX bit vector - 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available - 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available - 0xa, 0, ebx, 2, no_refcycle_evt , Reference cycles event not available - 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available - 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available - 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch instruction retired event not available - 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mispredict retired event not available - 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available + 0xa, 0, eax, 15:8, num_counters_gp , Number of general-purpose PMU counters per logical CPU + 0xa, 0, eax, 23:16, bit_width_gp , Bitwidth of PMU general-purpose counters + 0xa, 0, eax, 31:24, events_mask_len , Length of CPUID(0xa).EBX bit vector + 0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available + 0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available + 0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available + 0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available + 0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available + 0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available + 0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available + 0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available + 0xa, 0, ebx, 8, no_backend_bound , Topdown backend bound not available + 0xa, 0, ebx, 9, no_bad_speculation , Topdown bad speculation not available + 0xa, 0, ebx, 10, no_frontend_bound , Topdown frontend bound not available + 0xa, 0, ebx, 11, no_retiring , Topdown retiring not available + 0xa, 0, ebx, 12, no_lbr_inserts , LBR inserts not available 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap - 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters - 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters - 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation + 0xa, 0, edx, 4:0, num_counters_fixed , Number of fixed PMU counters + 0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth of PMU fixed counters + 0xa, 0, edx, 15, anythread_deprecation , AnyThread mode deprecation # Leaf BH -# CPUs v1 extended topology enumeration +# CPU extended topology v1 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain @@ -335,107 +341,109 @@ 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU # Leaf DH -# Processor extended state enumeration - - 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported - 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported - 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU registers) - 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U (bit 11) supported (CET user state) - 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S (bit 12) supported (CET supervisor state) - 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) - 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRSTOR area byte size, for XCR0 enabled features +# CPU extended state + + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 + 0xd, 0, eax, 1, xcr0_sse , XCR0.SSE + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS: MPX BND0-BND3 registers + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK: AVX-512 k0-k7 registers + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 registers + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 registers + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU: XSAVE PKRU registers + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U: CET user state + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S: CET supervisor state + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG: AMX can manage TILECONFIG + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA: AMX can manage TILEDATA + 0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XRSTOR area byte size, for XCR0 enabled features 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTOR area max byte size, all CPU features - 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling) + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP: Light-weight Profiling 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction 0xd, 1, eax, 1, xsavec , XSAVEC instruction 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR) - 0xd, 1, eax, 4, xfd , Extended feature disable support - 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled - 0xd, 1, ecx, 8, xss_pt , PT state, supported - 0xd, 1, ecx, 10, xss_pasid , PASID state, supported - 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported - 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported - 0xd, 1, ecx, 13, xss_hdc , HDC state, supported - 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported - 0xd, 1, ecx, 15, xss_lbr , LBR state, supported - 0xd, 1, ecx, 16, xss_hwp , HWP state, supported - 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes - 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes - 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit, otherwise XCR0 bit - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature XSAVE area is 64-byte aligned + 0xd, 1, eax, 4, xfd , Extended feature disable + 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xss , XSAVES/XSAVEC area byte size, for XCR0|XSS enabled features + 0xd, 1, ecx, 8, xss_pt , PT state + 0xd, 1, ecx, 10, xss_pasid , PASID state + 0xd, 1, ecx, 11, xss_cet_u , CET user state + 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state + 0xd, 1, ecx, 13, xss_hdc , HDC state + 0xd, 1, ecx, 14, xss_uintr , UINTR state + 0xd, 1, ecx, 15, xss_lbr , LBR state + 0xd, 1, ecx, 16, xss_hwp , HWP state + 0xd, 63:2, eax, 31:0, xsave_sz , Subleaf-N feature save area size, in bytes + 0xd, 63:2, ebx, 31:0, xsave_offset , Subleaf-N feature save area offset, in bytes + 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit (otherwise XCR0) + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N XSAVE area is 64-byte aligned # Leaf FH # Intel RDT / AMD PQoS resource monitoring - 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based) - 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported + 0xf, 0, ebx, 31:0, core_rmid_max , RMID max within this core (0-based) + 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based) 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit + 0xf, 1, eax, 9, io_rdt_cmt , non-CPU agent supporting Intel RDT CMT present + 0xf, 1, eax, 10, io_rdt_mbm , non-CPU agent supporting Intel RDT MBM present 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID - 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported - 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring supported - 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring supported + 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring + 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring + 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring # Leaf 10H -# Intel RDT / AMD PQoS allocation enumeration +# Intel RDT / AMD PQoS allocation - 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology supported - 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology supported - 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation supported + 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology + 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology + 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation - 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units + 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT allocation units bitmap 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent - 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritization) - 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supported - 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) supported + 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT Code and Data Prioritization + 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value + 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max Class of Service 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation - 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported + 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls 0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear - 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service supported + 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service # Leaf 12H -# Intel Software Guard Extensions (SGX) enumeration - - 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions supported - 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported - 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported - 0x12, 0, eax, 6, encls_leaves , ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported - 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported - 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN supported - 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA supported - 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: reporting #PF and #GP exceptions inside enclave supported - 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptions inside enclave supported +# Intel SGX (Software Guard Extensions) + + 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions + 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions + 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves + 0x12, 0, eax, 6, encls_leaves , ENCLS leaves + 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 + 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN + 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA + 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: Enclave #PF and #GP reporting + 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: Enclave #CP reporting 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2) 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2) - 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave initialized by EINIT) - 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave permits debugger read/write) - 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode) - 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (provisioning key available) - 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available) - 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET attributes) - 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separation and Sharing enabled) - 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications - 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported - 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported - 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) - 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) - 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) - 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) - 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type (dictates output layout) + 0x12, 1, eax, 0, secs_attr_init , Enclave initialized by EINIT + 0x12, 1, eax, 1, secs_attr_debug , Enclave permits debugger read/write + 0x12, 1, eax, 2, secs_attr_mode64bit , Enclave runs in 64-bit mode + 0x12, 1, eax, 4, secs_attr_provisionkey , Provisioning key + 0x12, 1, eax, 5, secs_attr_einittoken_key, EINIT token key + 0x12, 1, eax, 6, secs_attr_cet , CET attributes + 0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing + 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications + 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 + 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE + 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (AVX-512 k0-k7 registers) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZMM7/15 registers) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM31 registers) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (XSAVE PKRU registers) + 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (AMX can manage TILECONFIG) + 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (AMX can manage TILEDATA) + 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base address, bits[12:31] 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base address, bits[32:51] 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding @@ -443,44 +451,44 @@ 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51] # Leaf 14H -# Intel Processor Trace enumeration +# Intel Processor Trace 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum leaf 0x14 subleaf 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression - 0x14, 0, ebx, 4, ptwrite , PTWRITE support - 0x14, 0, ebx, 5, power_event_trace , Power Event Trace support - 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation support - 0x14, 0, ebx, 7, event_trace , Event Trace packet generation through IA32_RTIT_CTL.EventEn - 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable through IA32_RTIT_CTL.DisTNT - 0x14, 0, ecx, 0, topa_output , ToPA output scheme support + 0x14, 0, ebx, 4, ptwrite , PTWRITE instruction + 0x14, 0, ebx, 5, power_event_trace , Power Event Trace + 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation + 0x14, 0, ebx, 7, event_trace , Event Trace packet generation + 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable + 0x14, 0, ecx, 0, topa_output , ToPA output scheme 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries - 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported - 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output support + 0x14, 0, ecx, 2, single_range_output , Single-range output + 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included) - 0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Address Ranges - 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodings - 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold encodings - 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB frequency encodings + 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges + 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap + 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap + 0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap # Leaf 15H -# Intel TSC (Time Stamp Counter) enumeration +# Intel TSC (Time Stamp Counter) 0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio 0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz # Leaf 16H -# Intel processor frequency enumeration +# Intel processor frequency 0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz 0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz # Leaf 17H -# Intel SoC vendor attributes enumeration +# Intel SoC vendor attributes 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID @@ -493,32 +501,32 @@ 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15) # Leaf 18H -# Intel determenestic address translation (TLB) parameters +# Intel deterministic address translation (TLB) parameters 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum leaf 0x18 subleaf - 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported - 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported - 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported - 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/Soft) partitioning between logical CPUs sharing this structure + 0x18, 31:0, ebx, 0, tlb_4k_page , TLB supports 4KB-page entries + 0x18, 31:0, ebx, 1, tlb_2m_page , TLB supports 2MB-page entries + 0x18, 31:0, ebx, 2, tlb_4m_page , TLB supports 4MB-page entries + 0x18, 31:0, ebx, 3, tlb_1g_page , TLB supports 1GB-page entries + 0x18, 31:0, ebx, 10:8, hard_partitioning , Partitioning between logical CPUs 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity 0x18, 31:0, ecx, 31:0, n_sets , Number of sets 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based) - 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs for logical CPUs sharing this TLB - 1 + 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs - 1 # Leaf 19H -# Intel Key Locker enumeration +# Intel key locker - 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction supported - 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supported - 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supported - 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions supported - 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions supported - 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups supported - 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter supported - 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encoding 1) supported + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction + 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction + 0x19, 0, |