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| author | Daniel Golle <daniel@makrotopia.org> | 2026-03-26 05:09:35 +0000 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2026-04-28 19:05:42 -0700 |
| commit | 820ea6936b2d64d2171747ab37780ec9458a9236 (patch) | |
| tree | 55f18f6e17b5c0502358f5051e20fc5808bb03e9 /tools/perf/scripts/python | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
clk: mediatek: add MUX_CLR_SET macro
Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
a clock gate nor an update register.
Add a MUX_CLR_SET convenience macro that takes only the mux register
offsets, bit shift, and width, hardcoding upd_ofs = 0 and
upd_shift = -1 so callers cannot accidentally pass bogus sentinel
values to wrongly-typed fields.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions